Wade Fife
61ee0ddec3
This updates all RFNoC devices so that they get the RFNoC protocol version and CHDR width in the same way, from the output generated by the RFNoC image builder. Original-commit: 6f038dc2f69b38e715206b2e700fdd3a1bbc638e
165 lines
5.2 KiB
PHP
165 lines
5.2 KiB
PHP
#
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# Copyright 2008-2019 Ettus Research, a National Instruments Brand
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#
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##################################################
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# Project Setup
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##################################################
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# TOP_MODULE = <Input arg>
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# NAME = <Input arg>
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# PART_ID = <Input arg>
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# ARCH = <Input arg>
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##################################################
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# Include other makefiles
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##################################################
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BASE_DIR = $(abspath ..)
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IP_DIR = $(abspath ./ip)
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include $(BASE_DIR)/../tools/make/viv_design_builder.mak
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include $(IP_DIR)/Makefile.inc
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include coregen_dsp/Makefile.srcs
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include $(LIB_DIR)/ip/Makefile.inc
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include $(LIB_DIR)/hls/Makefile.inc
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include $(LIB_DIR)/control/Makefile.srcs
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include $(LIB_DIR)/fifo/Makefile.srcs
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include $(LIB_DIR)/simple_gemac/Makefile.srcs
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include $(LIB_DIR)/axi/Makefile.srcs
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include $(LIB_DIR)/timing/Makefile.srcs
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include $(LIB_DIR)/packet_proc/Makefile.srcs
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include $(LIB_DIR)/xge/Makefile.srcs
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include $(LIB_DIR)/xge_interface/Makefile.srcs
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include $(LIB_DIR)/dsp/Makefile.srcs
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include $(LIB_DIR)/axi/Makefile.srcs
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include $(LIB_DIR)/white_rabbit/wr_cores_v4_2/Makefile.srcs
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include $(LIB_DIR)/rfnoc/Makefile.srcs
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include $(BASE_DIR)/n3xx/dboards/rh/Makefile.srcs
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include $(BASE_DIR)/n3xx/dboards/mg/Makefile.srcs
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include $(BASE_DIR)/n3xx/dboards/common/Makefile.srcs
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# For sake of convenience, we include the Makefile.srcs for DRAM FIFO, DDC, and
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# DUC, Replay, and of course the radio. Any other block needs to use the
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# RFNOC_OOT_MAKEFILE_SRCS variable (see below).
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_axi_ram_fifo/Makefile.srcs
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_radio/Makefile.srcs
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_ddc/Makefile.srcs
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_duc/Makefile.srcs
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_replay/Makefile.srcs
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# If out-of-tree modules want to be compiled into this image, then they need to
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# pass in the RFNOC_OOT_MAKEFILE_SRCS as a list of Makefile.srcs files.
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# Those files need to amend the RFNOC_OOT_SRCS variable with a list of actual
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# source files.
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include $(RFNOC_OOT_MAKEFILE_SRCS)
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IMAGE_CORE ?= $(DEFAULT_RFNOC_IMAGE_CORE_FILE)
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EDGE_FILE ?= $(DEFAULT_EDGE_FILE)
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##################################################
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# Sources
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##################################################
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TOP_SRCS = \
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n3xx_core.v \
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n3xx_mgt_channel_wrapper.v \
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n3xx_mgt_wrapper.v \
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n3xx_mgt_io_core.v \
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n3xx_clocking.v \
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n3xx_db_fe_core.v \
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WrapBufg.vhd \
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$(IMAGE_CORE)
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MB_CLOCKS_XDC = $(abspath mb_clocks.xdc)
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MB_XDC = \
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mb_timing.xdc \
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mb_pins.xdc
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ifdef BUILD_WR
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MB_XDC += $(abspath n3xx_wr.xdc)
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TOP_SRCS += \
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n3xx_wr_top.vhd \
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n3xx_serial_dac.vhd \
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n3xx_serial_dac_arb.vhd
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endif
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ifdef BUILD_10G
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MB_XDC += $(abspath n310_10ge.xdc)
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endif
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ifdef BUILD_1G
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MB_XDC += $(abspath n310_1ge.xdc)
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endif
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ifdef BUILD_AURORA
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MB_XDC += $(abspath n310_aurora.xdc)
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endif
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ifndef NO_DRAM_FIFOS
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DRAM_SRCS = $(IP_DRAM_XCI_SRCS) $(abspath n310_dram.xdc)
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else
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DRAM_SRCS =
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endif
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ifdef N300
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DB_CLOCKS_XDC =
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DB_SRCS = $(MAGNESIUM_DB_TIMING_XDC) \
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$(MAGNESIUM_DB0_XDC) \
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$(MAGNESIUM_TOP_SRCS) $(MAGNESIUM_DB_SRCS)
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endif
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ifdef N310
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DB_CLOCKS_XDC =
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DB_SRCS = $(MAGNESIUM_DB_TIMING_XDC) \
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$(MAGNESIUM_DB0_XDC) $(MAGNESIUM_DB1_XDC) \
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$(MAGNESIUM_TOP_SRCS) $(MAGNESIUM_DB_SRCS)
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endif
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ifdef N320
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DB_CLOCKS_XDC = $(RHODIUM_DB_CLOCKS_XDC)
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DB_SRCS = $(RHODIUM_DB_XDC) \
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$(RHODIUM_TOP_SRCS) $(RHODIUM_DB_SRCS)
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endif
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DB_SRCS += $(DB_COMMON_SRCS)
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# The XDC files must be read in a specific order, motherboard first and then daughterboard,
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# and the clocking XDC files must be before other XDC files.
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# Outside of that, all the other sources can be read in any order desired.
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DESIGN_SRCS = $(MB_CLOCKS_XDC) $(DB_CLOCKS_XDC) $(abspath $(MB_XDC)) $(DB_SRCS) \
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$(abspath $(TOP_SRCS)) $(AXI_SRCS) $(FIFO_SRCS) \
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$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
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$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(COREGEN_DSP_SRCS) \
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$(UDP_SRCS) $(EXTRAM_SRCS) $(WISHBONE_SRCS) \
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$(XGE_SRCS) $(XGE_INTERFACE_SRCS) $(AURORA_PHY_SRCS) \
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$(TEN_GIGE_PHY_SRCS) $(ONE_GIGE_PHY_SRCS) \
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$(PACKET_PROC_SRCS) $(DSP_SRCS) $(DRAM_SRCS) \
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$(RADIO_SRCS) $(CAP_GEN_GENERIC_SRCS) $(IP_XCI_SRCS) $(BD_SRCS) \
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$(RFNOC_SRCS) $(RFNOC_OOT_SRCS) $(LIB_IP_XCI_SRCS) $(LIB_HLS_IP_SRCS) \
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$(WHITE_RABBIT_SRCS) \
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$(RFNOC_FRAMEWORK_SRCS) \
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$(RFNOC_BLOCK_AXI_RAM_FIFO_SRCS) \
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$(RFNOC_BLOCK_DUC_SRCS) $(RFNOC_BLOCK_DDC_SRCS) \
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$(RFNOC_BLOCK_RADIO_SRCS) \
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$(RFNOC_BLOCK_REPLAY_SRCS)
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EDGE_TBL_DEF="RFNOC_EDGE_TBL_FILE=$(call RESOLVE_PATH,$(EDGE_FILE))"
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IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(call RESOLVE_PATH,$(IMAGE_CORE:.v=.vh))"
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##################################################
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# Dependency Targets
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##################################################
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.SECONDEXPANSION:
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VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF) $(IMAGE_CORE_DEF)
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# DESIGN_SRCS and VERILOG_DEFS must be defined
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bin: .prereqs $$(DESIGN_SRCS) ip
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$(call BUILD_VIVADO_DESIGN,$(abspath ./build_n3xx.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID))
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synth: .prereqs $$(DESIGN_SRCS) ip
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$(call BUILD_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_synth.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID))
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rtl: .prereqs $$(DESIGN_SRCS) ip
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$(call CHECK_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_check_syntax.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID))
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.PHONY: bin rtl
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