Wade Fife
b2684c42a7
Change name in DRAM IP Makefile from IP_MIG_7SERIES_TG_SRCS to IP_DDR3_16BIT_TG_SRCS to match the naming of other variables. Original-commit: febf339e0df412e54cf43a204c280128d8ca1ec3
33 lines
1.3 KiB
Makefile
33 lines
1.3 KiB
Makefile
#
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# Copyright 2022 Ettus Research, a National Instruments Brand
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#
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include $(TOOLS_DIR)/make/viv_ip_builder.mak
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IP_DDR3_16BIT_SRCS = $(IP_BUILD_DIR)/ddr3_16bit/ddr3_16bit.xci
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IP_DDR3_16BIT_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr3_16bit/, \
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ddr3_16bit.xci.out \
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ddr3_16bit/user_design/rtl/ddr3_16bit.v \
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ddr3_16bit/user_design/rtl/ddr3_16bit_mig.v \
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)
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IP_DDR3_16BIT_TG_SRCS = $(addprefix $(IP_BUILD_DIR)/ddr3_16bit/, \
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ddr3_16bit/example_design/rtl/example_top.v \
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ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_axi4_tg.v \
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ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_axi4_wrapper.v \
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ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_cmd_prbs_gen_axi.v \
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ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_data_gen_chk.v \
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ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_tg.v \
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)
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IP_DDR3_16BIT_SIM_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr3_16bit/, \
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ddr3_16bit/example_design/sim/ddr3_model.sv \
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ddr3_16bit/example_design/sim/ddr3_model_parameters.vh \
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)
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$(IP_DDR3_16BIT_SRCS) $(IP_DDR3_16BIT_OUTS) : $(IP_DIR)/ddr3_16bit/ddr3_16bit.xci $(IP_DIR)/ddr3_16bit/mig_*.prj
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cp -f $(IP_DIR)/ddr3_16bit/mig_$(subst /,,$(PART_ID)).prj $(IP_DIR)/ddr3_16bit/mig_a.prj # Note: This won't allow parallel IP builds
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$(call BUILD_VIVADO_IP,ddr3_16bit,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
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rm -f $(IP_DIR)/ddr3_16bit/mig_a.prj
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