Wade Fife
c322899053
This adds DRAM support to E31x devices. Due to the size of the DDR3 memory controller, it is not enabled by default. You can include the memory controller IP in the build by adding the DRAM environment variable to your build. For example: DRAM=1 make E310_SG3 Original-commit: 788fef11ef890c6dcee3be495fc381bcf2990d3b
27 lines
968 B
Makefile
27 lines
968 B
Makefile
#
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# Copyright 2022 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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IP_AXI_INTER_2X64_128_ORIG_SRCS = $(addprefix $(IP_DIR)/axi_inter_2x64_128_bd/, \
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axi_inter_2x64_128_bd.tcl \
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)
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IP_AXI_INTER_2X64_128_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_2x64_128_bd/, \
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axi_inter_2x64_128_bd.tcl \
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)
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IP_AXI_INTER_2X64_128_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_2x64_128_bd/, \
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axi_inter_2x64_128_bd/axi_inter_2x64_128_bd.bd \
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)
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BD_AXI_INTER_2X64_128_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_inter_2x64_128_bd/, \
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axi_inter_2x64_128_bd.bd.out \
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axi_inter_2x64_128_bd/axi_inter_2x64_128_bd_ooc.xdc \
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axi_inter_2x64_128_bd/synth/axi_inter_2x64_128_bd.v \
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)
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$(IP_AXI_INTER_2X64_128_BD_SRCS) $(BD_AXI_INTER_2X64_128_BD_OUTS) $(IP_AXI_INTER_2X64_128_BDTCL_SRCS): $(IP_AXI_INTER_2X64_128_ORIG_SRCS)
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$(call BUILD_VIVADO_BDTCL,axi_inter_2x64_128_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi)
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