Wade Fife
6b19ec030c
This adds the NIPC parameter, which configures support for processing multiple items or samples per clock cycle. With this enabled, the FFT block can process at rates higher than 250 MSPS, such as 500 MSPS and beyond. Original-commit: fc76aa940e121fe1f85a3513f6d90df4667338cf
368 lines
16 KiB
Systemverilog
368 lines
16 KiB
Systemverilog
//
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// Copyright 2024 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: rfnoc_block_fft
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//
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// Description:
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//
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// RFNoC block for multichannel FFT/IFFT plus cyclic prefix insertion/removal.
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//
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// User Parameters:
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//
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// THIS_PORTID : Control crossbar port to which this block is connected
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// CHDR_W : AXIS-CHDR data bus width
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// MTU : Log2 of maximum transmission unit
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// NIPC : Number of samples/items per clock cycle to
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// process internally.
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// NUM_PORTS : Total number of FFT channels
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// NUM_CORES : Number of individual cores to instantiate.
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// Setting to 1 means all ports use a shared core
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// and therefore all ports share the same control
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// logic and all ports must be used simultaneously.
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// Setting to NUM_PORTS means that each port will
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// use its own core, and therefore each port can
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// be configured and used independently. NUM_PORTS
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// must be a multiple of NUM_CORES.
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// MAX_FFT_SIZE_LOG2 : Log2 of maximum configurable FFT size. That is,
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// the FFT size is exactly 2**fft_size_log2.
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// EN_CP_INSERTION : Controls whether to include the cyclic prefix
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// insertion logic. If included, EN_FFT_ORDER must
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// be 1.
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// EN_CP_REMOVAL : Controls whether to include the cyclic prefix
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// removal logic.
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// MAX_CP_LIST_LEN_INS_LOG2 : Log2 of max length of cyclic prefix insertion
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// list. Actual max is 2**MAX_CP_LIST_LEN_INS_LOG2.
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// MAX_CP_LIST_LEN_REM_LOG2 : Log2 of max length of cyclic prefix removal
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// list. Actual max is 2**MAX_CP_LIST_LEN_REM_LOG2.
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// CP_INSERTION_REPEAT : Enable repeating the CP insertion list. When 1,
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// the list repeats. When 0, CP insertion will
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// stop when the list is finished.
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// CP_REMOVAL_REPEAT : Enable repeating the CP removal list. When 1,
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// the list repeats. When 0, CP removal will
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// stop when the list is finished.
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// EN_FFT_BYPASS : Controls whether to include the FFT bypass logic.
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// EN_FFT_ORDER : Controls whether to include the FFT reorder logic.
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// EN_MAGNITUDE : Controls whether to include the magnitude
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// output calculation logic.
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// EN_MAGNITUDE_SQ : Controls whether to include the
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// magnitude-squared output calculation logic.
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// USE_APPROX_MAG : Controls whether to use the low-resource
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// approximate calculation (1) or the more exact
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// and more resource-intensive calculation (0) for
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// the magnitude calculation.
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//
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`default_nettype none
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module rfnoc_block_fft #(
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logic [9:0] THIS_PORTID = 10'd0,
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int CHDR_W = 64,
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logic [5:0] MTU = 6'd10,
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int NIPC = 1,
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int NUM_PORTS = 1,
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int NUM_CORES = 1,
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int MAX_FFT_SIZE_LOG2 = 10,
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bit EN_CP_REMOVAL = 1,
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bit EN_CP_INSERTION = 1,
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int MAX_CP_LIST_LEN_INS_LOG2 = 5,
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int MAX_CP_LIST_LEN_REM_LOG2 = 5,
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bit CP_INSERTION_REPEAT = 1,
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bit CP_REMOVAL_REPEAT = 1,
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bit EN_FFT_BYPASS = 0,
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bit EN_FFT_ORDER = 1,
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bit EN_MAGNITUDE = 0,
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bit EN_MAGNITUDE_SQ = 1,
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bit USE_APPROX_MAG = 1
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) (
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// RFNoC Framework Clocks and Resets
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input wire rfnoc_chdr_clk,
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input wire rfnoc_ctrl_clk,
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input wire ce_clk,
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// RFNoC Backend Interface
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input wire [ 511:0] rfnoc_core_config,
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output wire [ 511:0] rfnoc_core_status,
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// AXIS-CHDR Input Ports (from framework)
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input wire [CHDR_W*NUM_PORTS-1:0] s_rfnoc_chdr_tdata,
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input wire [ NUM_PORTS-1:0] s_rfnoc_chdr_tlast,
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input wire [ NUM_PORTS-1:0] s_rfnoc_chdr_tvalid,
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output wire [ NUM_PORTS-1:0] s_rfnoc_chdr_tready,
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// AXIS-CHDR Output Ports (to framework)
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output wire [CHDR_W*NUM_PORTS-1:0] m_rfnoc_chdr_tdata,
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output wire [ NUM_PORTS-1:0] m_rfnoc_chdr_tlast,
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output wire [ NUM_PORTS-1:0] m_rfnoc_chdr_tvalid,
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input wire [ NUM_PORTS-1:0] m_rfnoc_chdr_tready,
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// AXIS-Ctrl Input Port (from framework)
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input wire [ 31:0] s_rfnoc_ctrl_tdata,
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input wire s_rfnoc_ctrl_tlast,
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input wire s_rfnoc_ctrl_tvalid,
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output wire s_rfnoc_ctrl_tready,
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// AXIS-Ctrl Output Port (to framework)
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output wire [ 31:0] m_rfnoc_ctrl_tdata,
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output wire m_rfnoc_ctrl_tlast,
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output wire m_rfnoc_ctrl_tvalid,
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input wire m_rfnoc_ctrl_tready
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);
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`include "usrp_utils.svh"
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import ctrlport_pkg::*;
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import rfnoc_chdr_utils_pkg::*;
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import fft_core_regs_pkg::FFT_CORE_ADDR_W;
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localparam ITEM_W = 32;
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// Calculate the number of channels per core
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localparam int NCPC = NUM_PORTS / NUM_CORES;
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// We require each FFT core instance to have the same number of channels
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if (NUM_CORES * NCPC != NUM_PORTS) begin : check_num_ports_per_core
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$error("NUM_PORTS must be a multiple of NUM_CORES");
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end
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//---------------------------------------------------------------------------
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// Signal Declarations
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//---------------------------------------------------------------------------
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// Clocks and Resets
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logic ce_rst;
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logic ctrlport_req_wr;
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logic ctrlport_req_rd;
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logic [CTRLPORT_ADDR_W-1:0] ctrlport_req_addr;
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logic [CTRLPORT_DATA_W-1:0] ctrlport_req_data;
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logic ctrlport_resp_ack;
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logic [CTRLPORT_DATA_W-1:0] ctrlport_resp_data;
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logic [NUM_CORES-1:0][NCPC-1:0][ ITEM_W*NIPC-1:0] in_axis_tdata;
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logic [NUM_CORES-1:0][NCPC-1:0][ NIPC-1:0] in_axis_tkeep;
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logic [NUM_CORES-1:0][NCPC-1:0][ 0:0] in_axis_tlast;
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logic [NUM_CORES-1:0][NCPC-1:0][ 0:0] in_axis_tvalid;
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logic [NUM_CORES-1:0][NCPC-1:0][ 0:0] in_axis_tready;
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logic [NUM_CORES-1:0][NCPC-1:0][CHDR_TIMESTAMP_W-1:0] in_axis_ttimestamp;
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logic [NUM_CORES-1:0][NCPC-1:0][ 0:0] in_axis_thas_time;
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logic [NUM_CORES-1:0][NCPC-1:0][ CHDR_LENGTH_W-1:0] in_axis_tlength;
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logic [NUM_CORES-1:0][NCPC-1:0][ 0:0] in_axis_teov;
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logic [NUM_CORES-1:0][NCPC-1:0][ 0:0] in_axis_teob;
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logic [NUM_CORES-1:0][NCPC-1:0][ ITEM_W*NIPC-1:0] out_axis_tdata;
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logic [NUM_CORES-1:0][NCPC-1:0][ NIPC-1:0] out_axis_tkeep;
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logic [NUM_CORES-1:0][NCPC-1:0][ 0:0] out_axis_tlast;
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logic [NUM_CORES-1:0][NCPC-1:0][ 0:0] out_axis_tvalid;
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logic [NUM_CORES-1:0][NCPC-1:0][ 0:0] out_axis_tready;
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logic [NUM_CORES-1:0][NCPC-1:0][CHDR_TIMESTAMP_W-1:0] out_axis_ttimestamp;
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logic [NUM_CORES-1:0][NCPC-1:0][ 0:0] out_axis_thas_time;
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logic [NUM_CORES-1:0][NCPC-1:0][ CHDR_LENGTH_W-1:0] out_axis_tlength;
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logic [NUM_CORES-1:0][NCPC-1:0][ 0:0] out_axis_teov;
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logic [NUM_CORES-1:0][NCPC-1:0][ 0:0] out_axis_teob;
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//---------------------------------------------------------------------------
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// NoC Shell
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//---------------------------------------------------------------------------
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noc_shell_fft #(
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.CHDR_W (CHDR_W),
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.THIS_PORTID(THIS_PORTID),
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.MTU (MTU),
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.NUM_PORTS (NUM_PORTS),
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.NIPC (NIPC),
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.ITEM_W (ITEM_W)
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) noc_shell_fft_i (
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//---------------------
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// Framework Interface
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//---------------------
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// Clock Inputs
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.rfnoc_chdr_clk (rfnoc_chdr_clk),
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.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
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.ce_clk (ce_clk),
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// Reset Outputs
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.rfnoc_chdr_rst (),
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.rfnoc_ctrl_rst (),
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.ce_rst (ce_rst),
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// RFNoC Backend Interface
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.rfnoc_core_config (rfnoc_core_config),
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.rfnoc_core_status (rfnoc_core_status),
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// CHDR Input Ports (from framework)
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.s_rfnoc_chdr_tdata (s_rfnoc_chdr_tdata),
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.s_rfnoc_chdr_tlast (s_rfnoc_chdr_tlast),
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.s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid),
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.s_rfnoc_chdr_tready (s_rfnoc_chdr_tready),
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// CHDR Output Ports (to framework)
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.m_rfnoc_chdr_tdata (m_rfnoc_chdr_tdata),
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.m_rfnoc_chdr_tlast (m_rfnoc_chdr_tlast),
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.m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid),
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.m_rfnoc_chdr_tready (m_rfnoc_chdr_tready),
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// AXIS-Ctrl Input Port (from framework)
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.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata),
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.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast),
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.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid),
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.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready),
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// AXIS-Ctrl Output Port (to framework)
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.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata),
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.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast),
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.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid),
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.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready),
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//---------------------
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// Client Interface
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//---------------------
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// CtrlPort Clock and Reset
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.ctrlport_clk (),
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.ctrlport_rst (),
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// CtrlPort Master
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.m_ctrlport_req_wr (ctrlport_req_wr),
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.m_ctrlport_req_rd (ctrlport_req_rd),
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.m_ctrlport_req_addr (ctrlport_req_addr),
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.m_ctrlport_req_data (ctrlport_req_data),
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.m_ctrlport_resp_ack (ctrlport_resp_ack),
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.m_ctrlport_resp_data (ctrlport_resp_data),
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// AXI-Stream Clock and Reset
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.axis_data_clk (),
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.axis_data_rst (),
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// Data Stream to User Logic: in
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.m_in_axis_tdata (in_axis_tdata),
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.m_in_axis_tkeep (in_axis_tkeep),
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.m_in_axis_tlast (in_axis_tlast),
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.m_in_axis_tvalid (in_axis_tvalid),
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.m_in_axis_tready (in_axis_tready),
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.m_in_axis_ttimestamp (in_axis_ttimestamp),
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.m_in_axis_thas_time (in_axis_thas_time),
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.m_in_axis_tlength (in_axis_tlength),
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.m_in_axis_teov (in_axis_teov),
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.m_in_axis_teob (in_axis_teob),
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// Data Stream from User Logic: out
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.s_out_axis_tdata (out_axis_tdata),
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.s_out_axis_tkeep (out_axis_tkeep),
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.s_out_axis_tlast (out_axis_tlast),
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.s_out_axis_tvalid (out_axis_tvalid),
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.s_out_axis_tready (out_axis_tready),
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.s_out_axis_ttimestamp(out_axis_ttimestamp),
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.s_out_axis_thas_time (out_axis_thas_time),
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.s_out_axis_tlength (out_axis_tlength),
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.s_out_axis_teov (out_axis_teov),
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.s_out_axis_teob (out_axis_teob)
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);
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//---------------------------------------------------------------------------
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// CtrlPort Splitter
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//---------------------------------------------------------------------------
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logic [NUM_CORES-1:0][ 0:0] dec_ctrlport_req_wr;
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logic [NUM_CORES-1:0][ 0:0] dec_ctrlport_req_rd;
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logic [NUM_CORES-1:0][CTRLPORT_ADDR_W-1:0] dec_ctrlport_req_addr;
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logic [NUM_CORES-1:0][CTRLPORT_DATA_W-1:0] dec_ctrlport_req_data;
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logic [NUM_CORES-1:0][ 0:0] dec_ctrlport_resp_ack;
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logic [NUM_CORES-1:0][CTRLPORT_DATA_W-1:0] dec_ctrlport_resp_data;
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generate
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if (NUM_CORES > 1) begin : gen_ctrlport_decoder
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ctrlport_decoder #(
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.NUM_SLAVES (NUM_CORES),
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.BASE_ADDR (0),
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.SLAVE_ADDR_W (FFT_CORE_ADDR_W)
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) ctrlport_decoder_i (
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.ctrlport_clk (ce_clk),
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.ctrlport_rst (ce_rst),
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.s_ctrlport_req_wr (ctrlport_req_wr),
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.s_ctrlport_req_rd (ctrlport_req_rd),
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.s_ctrlport_req_addr (ctrlport_req_addr),
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.s_ctrlport_req_data (ctrlport_req_data),
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.s_ctrlport_req_byte_en ('1),
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.s_ctrlport_req_has_time ('0),
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.s_ctrlport_req_time ('0),
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.s_ctrlport_resp_ack (ctrlport_resp_ack),
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.s_ctrlport_resp_status (),
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.s_ctrlport_resp_data (ctrlport_resp_data),
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.m_ctrlport_req_wr (dec_ctrlport_req_wr),
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.m_ctrlport_req_rd (dec_ctrlport_req_rd),
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.m_ctrlport_req_addr (dec_ctrlport_req_addr),
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.m_ctrlport_req_data (dec_ctrlport_req_data),
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.m_ctrlport_req_byte_en (),
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.m_ctrlport_req_has_time (),
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.m_ctrlport_req_time (),
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.m_ctrlport_resp_ack (dec_ctrlport_resp_ack),
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.m_ctrlport_resp_status ('0),
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.m_ctrlport_resp_data (dec_ctrlport_resp_data)
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);
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end else begin : gen_no_decoder
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assign dec_ctrlport_req_wr = ctrlport_req_wr;
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assign dec_ctrlport_req_rd = ctrlport_req_rd;
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assign dec_ctrlport_req_addr = CTRLPORT_ADDR_W'(ctrlport_req_addr[FFT_CORE_ADDR_W-1:0]);
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assign dec_ctrlport_req_data = ctrlport_req_data;
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assign ctrlport_resp_ack = dec_ctrlport_resp_ack;
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assign ctrlport_resp_data = dec_ctrlport_resp_data;
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end
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endgenerate
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//---------------------------------------------------------------------------
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// FFT Core
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//---------------------------------------------------------------------------
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// Convert CHDR MTU to packet size in items
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localparam int MAX_PKT_SIZE_LOG2 = $clog2(2**MTU * CHDR_W/ITEM_W);
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for (genvar core_i = 0; core_i < NUM_CORES; core_i = core_i+1) begin : gen_fft_cores
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fft_core #(
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.NIPC (NIPC ),
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.NUM_CHAN (NCPC ),
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.NUM_CORES (NUM_CORES ),
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.MAX_PKT_SIZE_LOG2 (MAX_PKT_SIZE_LOG2 ),
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.MAX_FFT_SIZE_LOG2 (MAX_FFT_SIZE_LOG2 ),
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.EN_CP_REMOVAL (EN_CP_REMOVAL ),
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.EN_CP_INSERTION (EN_CP_INSERTION ),
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.MAX_CP_LIST_LEN_INS_LOG2(MAX_CP_LIST_LEN_INS_LOG2),
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.MAX_CP_LIST_LEN_REM_LOG2(MAX_CP_LIST_LEN_REM_LOG2),
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.CP_INSERTION_REPEAT (CP_INSERTION_REPEAT ),
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.CP_REMOVAL_REPEAT (CP_REMOVAL_REPEAT ),
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.EN_FFT_BYPASS (EN_FFT_BYPASS ),
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.EN_FFT_ORDER (EN_FFT_ORDER ),
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.EN_MAGNITUDE (EN_MAGNITUDE ),
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.EN_MAGNITUDE_SQ (EN_MAGNITUDE_SQ ),
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.USE_APPROX_MAG (USE_APPROX_MAG )
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) fft_core_i (
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.ce_clk (ce_clk),
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.ce_rst (ce_rst),
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.s_ctrlport_req_wr (dec_ctrlport_req_wr [core_i]),
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.s_ctrlport_req_rd (dec_ctrlport_req_rd [core_i]),
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.s_ctrlport_req_addr (dec_ctrlport_req_addr [core_i]),
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.s_ctrlport_req_data (dec_ctrlport_req_data [core_i]),
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.s_ctrlport_resp_ack (dec_ctrlport_resp_ack [core_i]),
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.s_ctrlport_resp_data (dec_ctrlport_resp_data[core_i]),
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.s_in_axis_tdata (in_axis_tdata [core_i]),
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.s_in_axis_tkeep (in_axis_tkeep [core_i]),
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.s_in_axis_tlast (in_axis_tlast [core_i]),
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.s_in_axis_tvalid (in_axis_tvalid [core_i]),
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.s_in_axis_tready (in_axis_tready [core_i]),
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.s_in_axis_ttimestamp (in_axis_ttimestamp [core_i]),
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.s_in_axis_thas_time (in_axis_thas_time [core_i]),
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.s_in_axis_tlength (in_axis_tlength [core_i]),
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.s_in_axis_teov (in_axis_teov [core_i]),
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.s_in_axis_teob (in_axis_teob [core_i]),
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.m_out_axis_tdata (out_axis_tdata [core_i]),
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.m_out_axis_tkeep (out_axis_tkeep [core_i]),
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.m_out_axis_tlast (out_axis_tlast [core_i]),
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.m_out_axis_tvalid (out_axis_tvalid [core_i]),
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.m_out_axis_tready (out_axis_tready [core_i]),
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.m_out_axis_ttimestamp(out_axis_ttimestamp [core_i]),
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.m_out_axis_thas_time (out_axis_thas_time [core_i]),
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.m_out_axis_tlength (out_axis_tlength [core_i]),
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.m_out_axis_teov (out_axis_teov [core_i]),
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.m_out_axis_teob (out_axis_teob [core_i])
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);
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end : gen_fft_cores
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endmodule : rfnoc_block_fft
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`default_nettype wire
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