a1d7c252c2
Co-authored-by: Cherwa Vang <cherwa.vang@ni.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Original-commit: 99b841c75aa91709090cbf4046bf51b7ffb4f612
31 lines
1.3 KiB
Plaintext
31 lines
1.3 KiB
Plaintext
# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 2017 Intel Corporation. All rights reserved.
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# Your use of Intel Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Intel Program License
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# Subscription Agreement, the Intel Quartus Prime License Agreement,
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# the Intel FPGA IP License Agreement, or other applicable license
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# agreement, including, without limitation, that your use is for
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# the sole purpose of programming logic devices manufactured by
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# Intel and sold by Intel or its authorized distributors. Please
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# refer to the applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus Prime
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# Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition
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# Date created = 17:19:38 August 16, 2019
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#
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# -------------------------------------------------------------------------- #
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QUARTUS_VERSION = "17.1"
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DATE = "17:19:38 August 16, 2019"
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# Revisions
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PROJECT_REVISION = "zbx_top_cpld"
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