Javier Valenzuela
a6fc53b4e6
The main changes included are: - Variant-dependent pin-out instantiation. - Update clocking scheme in top level file to include XO3 PLL - Add ability to shift outgoing data for the GPIO communication interface with the X410 FPGA. - Include project files required to build the XO3 variant of the ZBX CPLD. - Add build flow for Lattice Diamond designs. - Add ability to build XO3 variant of ZBX CPLD. Original-commit: 2c7813acb21383f302353a1b6cf57f0946fa0b6b
23 lines
693 B
Tcl
23 lines
693 B
Tcl
#
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# Copyright 2022 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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#
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# This file contains the sequence of steps required to
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# build and generate outputs for the ZBX CPLD, XO3 variant.
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# It is intended to be use as a parameter for
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# pnmainc (Diamond TCL console).
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# pnmainc.exe build.tcl > <LOG_FILE_NAME>
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prj_project open "zbx_top_cpld.ldf"
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prj_run Synthesis -impl impl1
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prj_run Translate -impl impl1
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prj_run Map -impl impl1
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prj_run PAR -impl impl1
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prj_run PAR -impl impl1 -task PARTrace
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prj_run Export -impl impl1 -task Bitgen
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prj_run Export -impl impl1 -task Jedecgen
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prj_run Export -impl impl1 -task Jedec4Xo3l
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prj_project close
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