20 lines
475 B
Systemverilog
20 lines
475 B
Systemverilog
//
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// Copyright 2023 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Header: rfnoc_image_core.vh (for n320)
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//
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// Description:
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//
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// This is the header file for the RFNoC Image Core.
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//
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// This file was automatically generated by the RFNoC image builder tool.
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// Re-running that tool will overwrite this file!
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//
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// Source: n320_bist_image_core.yml
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//
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`define CHDR_WIDTH 64
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`define RFNOC_PROTOVER { 8'd1, 8'd0 }
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