167 lines
4.5 KiB
Verilog
167 lines
4.5 KiB
Verilog
//
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// Copyright 2020 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Description:
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//
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// Windowing module. Multiplies each input packet by the coefficients loaded
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// into an internal memory.
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//
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// Parameters:
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//
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// WINDOW_SIZE : Sets the maximum window size to 2^WINDOW_SIZE samples.
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// COEFF_WIDTH : The bit width of coefficients.
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//
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module window #(
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parameter WINDOW_SIZE = 10,
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parameter COEFF_WIDTH = 16
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) (
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input wire clk,
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input wire rst,
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// Window size to use
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input wire [WINDOW_SIZE:0] window_size,
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// Coefficient input
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input wire [COEFF_WIDTH-1:0] m_axis_coeff_tdata,
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input wire m_axis_coeff_tlast,
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input wire m_axis_coeff_tvalid,
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output wire m_axis_coeff_tready,
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// Input data stream
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input wire [31:0] i_tdata,
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input wire i_tlast,
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input wire i_tvalid,
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output wire i_tready,
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// Output data stream
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output wire [31:0] o_tdata,
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output wire o_tlast,
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output wire o_tvalid,
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input wire o_tready
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);
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// Sample data stream (from i_tdata)
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wire [ 31:0] stream_tdata;
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wire stream_tlast;
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wire stream_tvalid;
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wire stream_tready;
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// RAM output data stream (saved coefficients)
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wire [ 15:0] ram_tdata;
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wire ram_tvalid;
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wire ram_tready;
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// Counter data stream (RAM address for coefficient lookup)
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wire [WINDOW_SIZE-1:0] count_tdata;
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wire count_tvalid;
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wire count_tready;
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// Flow control stream. This keeps the counter stream in sync with the
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// sample data stream.
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wire flow_tvalid;
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wire flow_tready;
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wire clear_counter;
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// Restart the address counter whenever we load a new set of coefficients.
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assign clear_counter = m_axis_coeff_tlast &
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m_axis_coeff_tvalid &
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m_axis_coeff_tready;
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// Split the incoming data stream into two
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split_stream_fifo #(
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.WIDTH (32),
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.ACTIVE_MASK (4'b0011)
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) split_stream_fifo_i (
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.clk (clk),
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.reset (rst),
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.clear (1'b0),
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.i_tdata (i_tdata),
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.i_tlast (i_tlast),
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.i_tvalid (i_tvalid),
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.i_tready (i_tready),
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.o0_tdata (stream_tdata),
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.o0_tlast (stream_tlast),
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.o0_tvalid (stream_tvalid),
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.o0_tready (stream_tready),
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.o1_tdata (),
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.o1_tlast (),
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.o1_tvalid (flow_tvalid),
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.o1_tready (flow_tready),
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.o2_tdata (),
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.o2_tlast (),
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.o2_tvalid (),
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.o2_tready (1'b0),
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.o3_tdata (),
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.o3_tlast (),
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.o3_tvalid (),
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.o3_tready (1'b0)
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);
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// Address generation
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counter #(
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.WIDTH (WINDOW_SIZE)
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) counter_i (
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.clk (clk),
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.reset (rst),
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.clear (clear_counter),
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.max (window_size),
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.i_tlast (1'b0),
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.i_tvalid (flow_tvalid),
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.i_tready (flow_tready),
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.o_tdata (count_tdata),
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.o_tlast (),
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.o_tvalid (count_tvalid),
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.o_tready (count_tready)
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);
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// RAM to store window coefficients
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ram_to_fifo #(
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.DWIDTH (COEFF_WIDTH),
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.AWIDTH (WINDOW_SIZE)
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) ram_to_fifo_i (
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.clk (clk),
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.reset (rst),
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.clear (1'b0),
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.config_tdata (m_axis_coeff_tdata),
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.config_tlast (m_axis_coeff_tlast),
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.config_tvalid (m_axis_coeff_tvalid),
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.config_tready (m_axis_coeff_tready),
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.i_tdata (count_tdata),
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.i_tlast (1'b0),
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.i_tvalid (count_tvalid),
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.i_tready (count_tready),
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.o_tdata (ram_tdata),
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.o_tlast (),
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.o_tvalid (ram_tvalid),
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.o_tready (ram_tready)
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);
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// Real by complex multiplier. This multiplier is configured for signed
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// fixed point with 15 fractional bits. For N fractional bits (a right-shift
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// by N in the multiplication result), set:
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// DROP_TOP_P = (WIDTH_REAL + WIDTH_CPLX - WIDTH_P + 5) - N
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mult_rc #(
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.WIDTH_REAL (COEFF_WIDTH),
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.WIDTH_CPLX (16),
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.WIDTH_P (16),
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.DROP_TOP_P (6)
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) mult_rc_i (
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.clk (clk),
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.reset (rst),
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.real_tdata (ram_tdata),
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.real_tlast (1'b0),
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.real_tvalid (ram_tvalid),
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.real_tready (ram_tready),
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.cplx_tdata (stream_tdata),
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.cplx_tlast (stream_tlast),
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.cplx_tvalid (stream_tvalid),
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.cplx_tready (stream_tready),
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.p_tdata (o_tdata),
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.p_tlast (o_tlast),
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.p_tvalid (o_tvalid),
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.p_tready (o_tready)
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);
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endmodule
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