Wade Fife
61ee0ddec3
This updates all RFNoC devices so that they get the RFNoC protocol version and CHDR width in the same way, from the output generated by the RFNoC image builder. Original-commit: 6f038dc2f69b38e715206b2e700fdd3a1bbc638e
137 lines
4.4 KiB
PHP
137 lines
4.4 KiB
PHP
#
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# Copyright 2008-2012 Ettus Research LLC
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#
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##################################################
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# Project Setup
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##################################################
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# TOP_MODULE = <Input arg>
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# NAME = <Input arg>
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# PART_ID = <Input arg>
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# ARCH = <Input arg>
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##################################################
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# Include other makefiles
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##################################################
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BASE_DIR = $(abspath ..)
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IP_DIR = $(abspath ./ip)
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include $(BASE_DIR)/../tools/make/viv_design_builder.mak
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include $(IP_DIR)/Makefile.inc
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include coregen_dsp/Makefile.srcs
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include $(LIB_DIR)/ip/Makefile.inc
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include $(LIB_DIR)/hls/Makefile.inc
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include $(LIB_DIR)/control/Makefile.srcs
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include $(LIB_DIR)/fifo/Makefile.srcs
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include $(LIB_DIR)/simple_gemac/Makefile.srcs
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include $(LIB_DIR)/timing/Makefile.srcs
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include $(LIB_DIR)/zpu/Makefile.srcs
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include $(LIB_DIR)/wishbone/Makefile.srcs
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include $(LIB_DIR)/packet_proc/Makefile.srcs
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include $(LIB_DIR)/xge/Makefile.srcs
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include $(LIB_DIR)/xge_interface/Makefile.srcs
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include $(LIB_DIR)/dsp/Makefile.srcs
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include $(LIB_DIR)/io_port2/Makefile.srcs
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include $(LIB_DIR)/axi/Makefile.srcs
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include $(LIB_DIR)/io_cap_gen/Makefile.srcs
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include $(LIB_DIR)/rfnoc/Makefile.srcs
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# For sake of convenience, we include the Makefile.srcs for DRAM FIFO, DDC, and
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# DUC, Replay, and of course the radio. Any other block needs to use the
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# RFNOC_OOT_MAKEFILE_SRCS variable (see below).
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_axi_ram_fifo/Makefile.srcs
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_radio/Makefile.srcs
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_ddc/Makefile.srcs
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_duc/Makefile.srcs
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_replay/Makefile.srcs
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# If out-of-tree modules want to be compiled into this image, then they need to
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# pass in the RFNOC_OOT_MAKEFILE_SRCS as a list of Makefile.srcs files.
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# Those files need to amend the RFNOC_OOT_SRCS variable with a list of actual
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# source files.
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-include $(RFNOC_OOT_MAKEFILE_SRCS)
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IMAGE_CORE ?= $(DEFAULT_RFNOC_IMAGE_CORE_FILE)
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EDGE_FILE ?= $(DEFAULT_EDGE_FILE)
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##################################################
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# Sources
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##################################################
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TOP_SRCS = \
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x300.v \
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x300_pcie_int.v \
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x300_core.v \
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x300_sfpp_io_core.v \
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x300_zpu_config.vhd \
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x300_eth_interface.v \
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nirio_chdr64_adapter.v \
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soft_ctrl.v \
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capture_ddrlvds.v \
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gen_ddrlvds.v \
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bus_int.v \
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x300.xdc \
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timing.xdc \
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$(IMAGE_CORE)
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ifdef BUILD_10G
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SFP_SERDES_SRCS += $(XGE_SRCS) $(XGE_INTERFACE_SRCS) $(abspath x300_10ge.xdc) $(TEN_GIGE_PHY_SRCS) $(IP_TEN_GIGE_PHY_XCI_SRCS)
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endif
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ifdef BUILD_1G
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SFP_SERDES_SRCS += $(abspath x300_1ge.xdc) $(ONE_GIGE_PHY_SRCS) $(IP_ONE_GIGE_PHY_XCI_SRCS)
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endif
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ifdef BUILD_AURORA
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SFP_SERDES_SRCS += $(abspath x300_aurora.xdc) $(AURORA_PHY_SRCS) $(IP_AURORA_XCI_SRCS)
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endif
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ifdef SFP0_10GBE
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SFP_SERDES_SRCS += $(abspath x300_10ge_port0.xdc)
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endif
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ifdef SFP1_10GBE
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SFP_SERDES_SRCS += $(abspath x300_10ge_port1.xdc)
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endif
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ifndef NO_DRAM_FIFOS
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DRAM_SRCS = $(IP_DRAM_XCI_SRCS) $(abspath x300_dram.xdc)
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else
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DRAM_SRCS =
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endif
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DESIGN_SRCS = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
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$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
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$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(COREGEN_DSP_SRCS) \
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$(UDP_SRCS) $(EXTRAM_SRCS) \
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$(ZPU_CORE_SRCS) $(WISHBONE_SRCS) \
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$(SFP_SERDES_SRCS) $(IOPORT2_SRCS) \
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$(PACKET_PROC_SRCS) $(DSP_SRCS) $(DRAM_SRCS) \
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$(AXI_SRCS) $(CAP_GEN_GENERIC_SRCS) $(IP_XCI_SRCS) $(BD_SRCS) \
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$(RFNOC_SRCS) $(LIB_IP_XCI_SRCS) \
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$(RFNOC_FRAMEWORK_SRCS) \
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$(RFNOC_BLOCK_DUC_SRCS) $(RFNOC_BLOCK_DDC_SRCS) $(RFNOC_BLOCK_RADIO_SRCS) \
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$(RFNOC_BLOCK_AXI_RAM_FIFO_SRCS) \
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$(RFNOC_BLOCK_REPLAY_SRCS) \
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$(RFNOC_OOT_SRCS)
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EDGE_TBL_DEF="RFNOC_EDGE_TBL_FILE=$(call RESOLVE_PATH,$(EDGE_FILE))"
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IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(DEFAULT_RFNOC_IMAGE_CORE_FILE:.v=.vh)"
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##################################################
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# Dependency Targets
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##################################################
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.SECONDEXPANSION:
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VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF) $(IMAGE_CORE_DEF)
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# DESIGN_SRCS and VERILOG_DEFS must be defined
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bin: .prereqs $$(DESIGN_SRCS) ip
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$(call BUILD_VIVADO_DESIGN,$(abspath ./build_x300.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID))
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synth: .prereqs $$(DESIGN_SRCS) ip
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$(call BUILD_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_synth.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID))
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rtl: .prereqs $$(DESIGN_SRCS) ip
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$(call CHECK_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_check_syntax.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID))
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.PHONY: bin rtl
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