74 lines
2.7 KiB
Verilog
74 lines
2.7 KiB
Verilog
//
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// Copyright 2021 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: ctrlport_window
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//
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// Description:
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// Copy requests from slave to master interface when s_ctrlport_req_addr is in
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// address range specified by BASE_ADDRESS and WINDOW_SIZE. The modules does
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// not use any registers and therefore does not need ctrlport_clk and
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// ctrlport_rst.
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//
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`default_nettype none
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module ctrlport_window #(
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parameter BASE_ADDRESS = 0,
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parameter WINDOW_SIZE = 32
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) (
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// Slave Interface
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input wire s_ctrlport_req_wr,
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input wire s_ctrlport_req_rd,
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input wire [19:0] s_ctrlport_req_addr,
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input wire [ 9:0] s_ctrlport_req_portid,
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input wire [15:0] s_ctrlport_req_rem_epid,
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input wire [ 9:0] s_ctrlport_req_rem_portid,
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input wire [31:0] s_ctrlport_req_data,
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input wire [ 3:0] s_ctrlport_req_byte_en,
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input wire s_ctrlport_req_has_time,
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input wire [63:0] s_ctrlport_req_time,
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output wire s_ctrlport_resp_ack,
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output wire [ 1:0] s_ctrlport_resp_status,
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output wire [31:0] s_ctrlport_resp_data,
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// Master Interface
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output wire m_ctrlport_req_wr,
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output wire m_ctrlport_req_rd,
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output wire [19:0] m_ctrlport_req_addr,
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output wire [ 9:0] m_ctrlport_req_portid,
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output wire [15:0] m_ctrlport_req_rem_epid,
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output wire [ 9:0] m_ctrlport_req_rem_portid,
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output wire [31:0] m_ctrlport_req_data,
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output wire [ 3:0] m_ctrlport_req_byte_en,
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output wire m_ctrlport_req_has_time,
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output wire [63:0] m_ctrlport_req_time,
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input wire m_ctrlport_resp_ack,
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input wire [ 1:0] m_ctrlport_resp_status,
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input wire [31:0] m_ctrlport_resp_data
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);
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// Mask write and read flag
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wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + WINDOW_SIZE);
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assign m_ctrlport_req_wr = s_ctrlport_req_wr & address_in_range;
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assign m_ctrlport_req_rd = s_ctrlport_req_rd & address_in_range;
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// Forward all other signals untouched.
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assign m_ctrlport_req_addr = s_ctrlport_req_addr;
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assign m_ctrlport_req_portid = s_ctrlport_req_portid;
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assign m_ctrlport_req_rem_epid = s_ctrlport_req_rem_epid;
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assign m_ctrlport_req_rem_portid = s_ctrlport_req_rem_portid;
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assign m_ctrlport_req_data = s_ctrlport_req_data;
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assign m_ctrlport_req_byte_en = s_ctrlport_req_byte_en;
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assign m_ctrlport_req_has_time = s_ctrlport_req_has_time;
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assign m_ctrlport_req_time = s_ctrlport_req_time;
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assign s_ctrlport_resp_ack = m_ctrlport_resp_ack;
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assign s_ctrlport_resp_status = m_ctrlport_resp_status;
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assign s_ctrlport_resp_data = m_ctrlport_resp_data;
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endmodule
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`default_nettype wire
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