Javier Valenzuela
a6fc53b4e6
The main changes included are: - Variant-dependent pin-out instantiation. - Update clocking scheme in top level file to include XO3 PLL - Add ability to shift outgoing data for the GPIO communication interface with the X410 FPGA. - Include project files required to build the XO3 variant of the ZBX CPLD. - Add build flow for Lattice Diamond designs. - Add ability to build XO3 variant of ZBX CPLD. Original-commit: 2c7813acb21383f302353a1b6cf57f0946fa0b6b
88 lines
1.4 KiB
Plaintext
88 lines
1.4 KiB
Plaintext
[Device]
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Family=machxo3lf
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PartType=LCMXO3LF-9400C
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PartName=LCMXO3LF-9400C-6BG256I
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SpeedGrade=6
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Package=CABGA256
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OperatingCondition=IND
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Status=S
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[IP]
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VendorName=Lattice Semiconductor Corporation
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CoreType=LPM
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CoreStatus=Demo
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CoreName=PLL
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CoreRevision=5.8
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ModuleName=pll
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SourceFormat=Verilog HDL
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ParameterFileVersion=1.0
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Date=03/03/2022
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Time=14:15:48
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[Parameters]
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Verilog=1
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VHDL=0
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EDIF=1
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Destination=Synplicity
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Expression=None
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Order=None
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IO=0
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mode=Frequency
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CLKI=64
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CLKI_DIV=1
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BW=6.139
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VCO=512.000
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fb_mode=CLKOP
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CLKFB_DIV=1
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FRACN_ENABLE=0
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FRACN_DIV=0
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DynamicPhase=STATIC
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ClkEnable=1
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Standby=0
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Enable_sel=0
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PLLRst=0
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PLLMRst=0
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ClkOS2Rst=0
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ClkOS3Rst=0
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LockSig=1
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LockStk=0
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WBProt=0
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OPBypass=0
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OPUseDiv=0
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CLKOP_DIV=8
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FREQ_PIN_CLKOP=64
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OP_Tol=0.0
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CLKOP_AFREQ=64.000000
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CLKOP_PHASEADJ=0
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CLKOP_TRIM_POL=Rising
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CLKOP_TRIM_DELAY=0
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EnCLKOS=1
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OSBypass=0
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OSUseDiv=0
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CLKOS_DIV=8
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FREQ_PIN_CLKOS=64
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OS_Tol=0.0
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CLKOS_AFREQ=64.000000
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CLKOS_PHASEADJ=225
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CLKOS_TRIM_POL=Rising
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CLKOS_TRIM_DELAY=0
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EnCLKOS2=0
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OS2Bypass=0
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OS2UseDiv=0
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CLKOS2_DIV=1
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FREQ_PIN_CLKOS2=64
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OS2_Tol=0.0
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CLKOS2_AFREQ=64.000000
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CLKOS2_PHASEADJ=225
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EnCLKOS3=0
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OS3Bypass=0
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OS3UseDiv=0
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CLKOS3_DIV=1
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FREQ_PIN_CLKOS3=100
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OS3_Tol=0.0
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CLKOS3_AFREQ=
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CLKOS3_PHASEADJ=0
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[Command]
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cmd_line= -w -n pll -lang verilog -synth synplify -arch xo3c00f -type pll -fin 64 -fclkop 64 -fclkop_tol 0.0 -fclkos 64 -fclkos_tol 0.0 -trimp 0 -phasep 0 -trimp_r -trims 0 -phases 225 -trims_r -phase_cntl STATIC -enable_ports -fb_mode 1 -lock
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