232 lines
7.3 KiB
Verilog
232 lines
7.3 KiB
Verilog
//
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// Copyright 2021 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: ps_power_regs
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//
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// Description:
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//
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// Registers to control power supplies on the motherboard.
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//
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// Parameters:
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//
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// BASE_ADDRESS : Base address for CtrlPort registers.
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// NUM_ADDRESSES : Number of bytes of address space to use.
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//
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`default_nettype none
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module ps_power_regs #(
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parameter BASE_ADDRESS = 0,
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parameter NUM_ADDRESSES = 32
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) (
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input wire ctrlport_clk,
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input wire ctrlport_rst,
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// Request
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input wire s_ctrlport_req_wr,
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input wire s_ctrlport_req_rd,
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input wire [19:0] s_ctrlport_req_addr,
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input wire [31:0] s_ctrlport_req_data,
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// Response
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output reg s_ctrlport_resp_ack,
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output reg [ 1:0] s_ctrlport_resp_status,
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output reg [31:0] s_ctrlport_resp_data,
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// iPass
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output reg ipass_power_disable = 1'b0,
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input wire [ 1:0] ipass_power_fault_n,
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// Oscillators
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output reg osc_100_en,
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output reg osc_122_88_en
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);
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`include "../regmap/ps_power_regmap_utils.vh"
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`include "../../../../lib/rfnoc/core/ctrlport.vh"
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//----------------------------------------------------------
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// Address Calculation
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//----------------------------------------------------------
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wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) &&
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(s_ctrlport_req_addr < BASE_ADDRESS + NUM_ADDRESSES);
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//----------------------------------------------------------
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// Internal Registers
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//----------------------------------------------------------
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reg [1:0] ipass_power_sticky = 2'b00;
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reg [1:0] ipass_clear_sticky = 2'b00;
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//----------------------------------------------------------
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// Handling of ControlPort Requests
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//----------------------------------------------------------
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always @(posedge ctrlport_clk) begin
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// Reset internal registers and responses
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if (ctrlport_rst) begin
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ipass_power_disable <= 1'b0;
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s_ctrlport_resp_ack <= 1'b0;
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s_ctrlport_resp_status <= CTRL_STS_OKAY;
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s_ctrlport_resp_data <= {CTRLPORT_ADDR_W {1'bx}};
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osc_100_en <= 1'b0;
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osc_122_88_en <= 1'b0;
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end else begin
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// Default assignments
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ipass_clear_sticky <= 2'b00;
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// Write requests
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if (s_ctrlport_req_wr) begin
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// Always issue an ack and no data
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s_ctrlport_resp_ack <= 1'b1;
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s_ctrlport_resp_status <= CTRL_STS_OKAY;
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s_ctrlport_resp_data <= {CTRLPORT_ADDR_W {1'bx}};
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case (s_ctrlport_req_addr)
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BASE_ADDRESS + IPASS_POWER_REG: begin
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ipass_power_disable <= s_ctrlport_req_data[IPASS_DISABLE_POWER_BIT];
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ipass_clear_sticky[0] <= s_ctrlport_req_data[IPASS_CLEAR_POWER_FAULT0];
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ipass_clear_sticky[1] <= s_ctrlport_req_data[IPASS_CLEAR_POWER_FAULT1];
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end
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BASE_ADDRESS + OSC_POWER_REG: begin
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osc_100_en <= s_ctrlport_req_data[OSC_100];
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osc_122_88_en <= s_ctrlport_req_data[OSC_122_88];
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end
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// Error on undefined address
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default: begin
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if (address_in_range) begin
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s_ctrlport_resp_status <= CTRL_STS_CMDERR;
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// No response if out of range
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end else begin
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s_ctrlport_resp_ack <= 1'b0;
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end
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end
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endcase
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// Read request
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end else if (s_ctrlport_req_rd) begin
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// Default assumption: valid request
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s_ctrlport_resp_ack <= 1'b1;
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s_ctrlport_resp_status <= CTRL_STS_OKAY;
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s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'b0}};
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case (s_ctrlport_req_addr)
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BASE_ADDRESS + IPASS_POWER_REG: begin
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s_ctrlport_resp_data[IPASS_DISABLE_POWER_BIT] <= ipass_power_disable;
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s_ctrlport_resp_data[IPASS_POWER_FAULT0] <= ipass_power_sticky[0];
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s_ctrlport_resp_data[IPASS_POWER_FAULT1] <= ipass_power_sticky[1];
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end
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BASE_ADDRESS + OSC_POWER_REG: begin
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s_ctrlport_resp_data[OSC_100] <= osc_100_en;
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s_ctrlport_resp_data[OSC_122_88] <= osc_122_88_en;
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end
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// Error on undefined address
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default: begin
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s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'bx}};
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if (address_in_range) begin
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s_ctrlport_resp_status <= CTRL_STS_CMDERR;
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// No response if out of range
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end else begin
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s_ctrlport_resp_ack <= 1'b0;
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end
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end
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endcase
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// No request
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end else begin
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s_ctrlport_resp_ack <= 1'b0;
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end
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end
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end
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//----------------------------------------------------------
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// Sticky Logic of Power Registers
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//----------------------------------------------------------
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// Synchronize asynchronous inputs
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wire [1:0] ipass_power_fault_lcl_n;
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synchronizer #(
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.WIDTH (2),
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.STAGES (2),
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.INITIAL_VAL (1'b0),
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.FALSE_PATH_TO_IN (1)
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) power_fault_sync (
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.clk (ctrlport_clk),
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.rst (ctrlport_rst),
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.in (ipass_power_fault_n),
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.out (ipass_power_fault_lcl_n)
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);
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always @(posedge ctrlport_clk) begin
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if (ctrlport_rst) begin
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ipass_power_sticky <= 2'b00;
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end else begin
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// Keep value if not cleared or set in case of fault
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ipass_power_sticky <= (ipass_power_sticky & ~ipass_clear_sticky) | ~ipass_power_fault_lcl_n;
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end
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end
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endmodule
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`default_nettype wire
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//XmlParse xml_on
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//<regmap name="PS_POWER_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
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// <group name="PS_POWER_REGS">
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// <info>
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// Registers to control power supplies on the motherboard.
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// </info>
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//
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// <register name="IPASS_POWER_REG" offset="0x00" size="32">
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// <info>Controls the power supplies for the iPass connectors.</info>
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// <bitfield name="IPASS_DISABLE_POWER_BIT" range="0">
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// <info>Set to 1 to disable power for both iPass connectors.</info>
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// </bitfield>
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// <bitfield name="IPASS_CLEAR_POWER_FAULT0" range="30" readable="false">
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// <info>Clear @.IPASS_POWER_FAULT0.</info>
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// </bitfield>
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// <bitfield name="IPASS_CLEAR_POWER_FAULT1" range="31" readable="false">
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// <info>Clear @.IPASS_POWER_FAULT1.</info>
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// </bitfield>
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// <bitfield name="IPASS_POWER_FAULT0" range="30" writable="false">
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// <info>
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// Asserted signal indicates a power fault in power switch for iPass
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// connector 0. Sticky bit. Asserted on occurrence. Reset using
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// @.IPASS_CLEAR_POWER_FAULT0.
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// </info>
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// </bitfield>
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// <bitfield name="IPASS_POWER_FAULT1" range="31" writable="false">
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// <info>
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// Asserted signal indicates a power fault in power switch for iPass
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// connector 1. Sticky bit. Asserted on occurrence. Reset using
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// @.IPASS_CLEAR_POWER_FAULT1.
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// </info>
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// </bitfield>
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// </register>
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//
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// <register name="OSC_POWER_REG" offset="0x04" size="32">
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// <info>Controls the power supplies for the oscillators.</info>
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// <bitfield name="OSC_100" range="0">
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// <info>Enables 5V power switch for the 100 MHz oscillator.</info>
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// </bitfield>
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// <bitfield name="OSC_122_88" range="1">
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// <info>Enables 5V power switch for the 122.88 MHz oscillator.</info>
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// </bitfield>
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// </register>
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// </group>
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//</regmap>
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//XmlParse xml_off
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