Ryan Marlow
a90444c784
Module description: Clock divider. Generates an output clock that is 1/N times the frequency of the input clock. Original-commit: 71bdcd22f07162687771d374178ad0372783bd45
54 lines
1.0 KiB
Verilog
54 lines
1.0 KiB
Verilog
//
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// Copyright 2022 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: clock_div
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//
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// Description:
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// Clock divider. Generates an output clock that is 1/N times the frequency
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// of the input clock.
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//
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// Parameters:
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//
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// N : Even number to divide clock by
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//
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module clock_div #(
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parameter N = 8'h1
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) (
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// Input Clock and reset
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input wire clk_in,
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input wire clk_in_rst,
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// Request
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output reg clk_out
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);
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localparam NDIV2 = N/2;
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localparam WIDTH = $clog2(NDIV2);
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reg [WIDTH-1:0] div_ctr;
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wire [WIDTH-1:0] next_div_ctr;
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//errors if N is not even
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if (N % 2 != 0) begin : gen_assertion
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ERROR_N_must_be_even();
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end
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always @(posedge clk_in) begin
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if(clk_in_rst) begin
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div_ctr <= 0;
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clk_out <= 0;
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end else if (next_div_ctr == NDIV2) begin
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div_ctr <= 0;
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clk_out <= ~clk_out;
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end else begin
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div_ctr <= next_div_ctr;
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end
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end
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assign next_div_ctr = div_ctr + 1;
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endmodule
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