37 lines
1.5 KiB
Systemverilog
37 lines
1.5 KiB
Systemverilog
//
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// Copyright 2022 Ettus Research, A National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: radio_ctrlport_regmap_utils.vh
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// Description:
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// The constants in this file are autogenerated by XmlParse.
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//===============================================================================
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// A numerically ordered list of registers and their HDL source files
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//===============================================================================
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// DB_WINDOW : 0x0 (x4xx_core_common.v)
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// RFDC_TIMING_WINDOW : 0x8000 (x4xx_core_common.v)
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// DIO_WINDOW : 0xC000 (x4xx_core_common.v)
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//===============================================================================
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// RegTypes
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//===============================================================================
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//===============================================================================
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// Register Group RADIO_CTRLPORT_WINDOWS
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//===============================================================================
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// DB_WINDOW Window (from x4xx_core_common.v)
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localparam DB_WINDOW = 'h0; // Window Offset
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localparam DB_WINDOW_SIZE = 'h8000; // size in bytes
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// RFDC_TIMING_WINDOW Window (from x4xx_core_common.v)
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localparam RFDC_TIMING_WINDOW = 'h8000; // Window Offset
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localparam RFDC_TIMING_WINDOW_SIZE = 'h4000; // size in bytes
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// DIO_WINDOW Window (from x4xx_core_common.v)
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localparam DIO_WINDOW = 'hC000; // Window Offset
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localparam DIO_WINDOW_SIZE = 'h4000; // size in bytes
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