Wade Fife
c322899053
This adds DRAM support to E31x devices. Due to the size of the DDR3 memory controller, it is not enabled by default. You can include the memory controller IP in the build by adding the DRAM environment variable to your build. For example: DRAM=1 make E310_SG3 Original-commit: 788fef11ef890c6dcee3be495fc381bcf2990d3b
70 lines
2.0 KiB
Makefile
70 lines
2.0 KiB
Makefile
#
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# Copyright 2014 Ettus Research
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#
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#include $(IP_DIR)/axi4_dualport_sram/Makefile.inc
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#include $(IP_DIR)/axi64_4k_2clk_fifo/Makefile.inc
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#include $(IP_DIR)/axi64_8k_2clk_fifo/Makefile.inc
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#include $(IP_DIR)/axi_intercon_4x64_256_bd/Makefile.inc
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#include $(IP_DIR)/ddr3_32bit/Makefile.inc
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include $(IP_DIR)/fifo_4k_2clk/Makefile.inc
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include $(IP_DIR)/fifo_short_2clk/Makefile.inc
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#include $(IP_DIR)/input_sample_fifo/Makefile.inc
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#include $(IP_DIR)/misc_clock_gen/Makefile.inc
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#include $(IP_DIR)/axi3_to_axi4lite_protocol_converter/Makefile.inc
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#include $(IP_DIR)/axis_fifo_to_axi4lite/Makefile.inc
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#include $(IP_DIR)/axi4_to_axi3_protocol_converter_32/Makefile.inc
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#include $(IP_DIR)/axi4_to_axi3_protocol_converter_64/Makefile.inc
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include $(IP_DIR)/e31x_ps_bd/Makefile.inc
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include $(IP_DIR)/ddr3_16bit/Makefile.inc
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include $(IP_DIR)/axi_inter_2x64_128_bd/Makefile.inc
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BD_SRCS = \
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$(IP_AXI_INTER_2X64_128_BD_SRCS) \
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$(IP_E31X_PS_BD_SRCS)
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IP_XCI_SRCS = \
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$(IP_FIFO_SHORT_2CLK_SRCS) \
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$(IP_AXI64_4K_2CLK_FIFO_SRCS) \
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$(IP_AXI64_8K_2CLK_FIFO_SRCS) \
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$(IP_MIG_7SERIES_0_SRCS) \
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$(IP_FIFO_4K_2CLK_SRCS) \
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#$(IP_AXI4_BRAM_SRCS) \
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#$(IP_AXI3_TO_AXI4LITE_PROTOCOL_CONVERTER_SRCS) \
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#$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_32_SRCS) \
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#$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_64_SRCS) \
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#$(IP_AXIS_FIFO_TO_AXI4LITE_SRCS) \
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#$(IP_MISC_CLOCK_GEN_SRCS) \
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IP_DRAM_XCI_SRCS = \
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$(IP_DDR3_16BIT_SRCS)
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## Currently unused
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## $(IP_INPUT_SAMPLE_FIFO_SRCS) \
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IP_SYNTH_OUTPUTS = \
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$(IP_FIFO_SHORT_2CLK_OUTS) \
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$(IP_AXI64_4K_2CLK_FIFO_OUTS) \
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$(IP_AXI64_8K_2CLK_FIFO_OUTS) \
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$(IP_FIFO_4K_2CLK_OUTS) \
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$(IP_MIG_7SERIES_0_OUTS) \
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#$(IP_AXI4_BRAM_OUTS) \
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#$(IP_AXI3_TO_AXI4LITE_PROTOCOL_CONVERTER_OUTS) \
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#$(IP_AXI_INTERCONNECT_OUTS) \
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#$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_32_OUTS) \
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#$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_64_OUTS) \
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#$(IP_AXIS_FIFO_TO_AXI4LITE_OUTS) \
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BD_OUTPUTS = \
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$(IP_AXI_INTER_2X64_128_BD_OUTS) \
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$(IP_E31X_PS_BD_OUTS)
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# Currently unused
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# $(IP_INPUT_SAMPLE_FIFO_OUTS) \
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# $(IP_AXI_INTERCON_4X64_128_OUTS) \
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ip: $(IP_SYNTH_OUTPUTS) $(BD_OUTPUTS)
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.PHONY: ip
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