93 lines
3.2 KiB
VHDL
93 lines
3.2 KiB
VHDL
--
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-- Copyright 2022 Ettus Research, a National Instruments Brand
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--
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-- SPDX-License-Identifier: LGPL-3.0-or-later
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--
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-- Module: PcieCmiWrapper
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--
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-- Description:
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--
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-- This is an automatically generated file.
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-- Do not modify this file directly!
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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--synopsys translate_off
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--For synthesis, netlist comes from an qxp and there is no external library
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--For simulation in client, netlist comes from PcieCmiLib external library
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--For simulation in dev branch, netlist comes from work library.
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--Binding will work fine in both simulation cases as long as PcieCmi is compiled
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-- to either library. In dev branch PcieCmiLib will be an empty library just so
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-- ModelSim doesn't complain.
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library PcieCmiLib;
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--synopsys translate_on
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entity PcieCmiWrapper is
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generic (
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kSimulation : natural := 0 -- set to 1 to speedup simulation
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);
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port (
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Clk : in std_logic; -- 40 MHz clock
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acReset : in std_logic;
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cSerialNumber : in std_logic_vector(39 downto 0);
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cBoardIsReady : in std_logic;
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cCmiReset : out std_logic;
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cOtherSideDetected : out std_logic;
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aCblPrsnt_n : in std_logic;
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aSdaIn : in std_logic;
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aSdaOut : out std_logic;
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aSclIn : in std_logic;
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aSclOut : out std_logic
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);
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end PcieCmiWrapper;
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architecture rtl of PcieCmiWrapper is
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component PcieCmi
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generic (kSimulation : natural := 0);
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port (
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Clk : in std_logic;
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acReset : in std_logic;
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cSerialNumber : in std_logic_vector(39 downto 0);
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cBoardIsReady : in std_logic;
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cCmiReset : out std_logic;
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cOtherSideDetected : out std_logic;
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aCblPrsnt_n : in std_logic;
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aSdaIn : in std_logic;
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aSdaOut : out std_logic;
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aSclIn : in std_logic;
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aSclOut : out std_logic);
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end component;
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begin
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-- Just forward all signals to lower level entity.
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-- Leave the simulation generic in place as it important to be able to
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-- simulate the netlist in reasonable time. For the synthesis in the client
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-- the generic is ignored as the netlist is translated with kSimulation set to
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-- default value and "overwrites" it.
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--vhook PcieCmi
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PcieCmix: PcieCmi
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generic map (kSimulation => kSimulation) --natural:=0
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port map (
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Clk => Clk, --in std_logic
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acReset => acReset, --in std_logic
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cSerialNumber => cSerialNumber, --in std_logic_vector(39:0)
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cBoardIsReady => cBoardIsReady, --in std_logic
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cCmiReset => cCmiReset, --out std_logic
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cOtherSideDetected => cOtherSideDetected, --out std_logic
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aCblPrsnt_n => aCblPrsnt_n, --in std_logic
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aSdaIn => aSdaIn, --in std_logic
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aSdaOut => aSdaOut, --out std_logic
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aSclIn => aSclIn, --in std_logic
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aSclOut => aSclOut); --out std_logic
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end architecture rtl; |