Wade Fife b2684c42a7 fpga: e31x: Fix DRAM traffic gen IP name ...

Change name in DRAM IP Makefile from IP_MIG_7SERIES_TG_SRCS to
IP_DDR3_16BIT_TG_SRCS to match the naming of other variables.


Original-commit: febf339e0df412e54cf43a204c280128d8ca1ec3

2022-03-23 08:55:36 -05:00

..

axi_inter_2x64_128_bd

fpga: e31x: Add DRAM support

2022-02-10 18:13:44 -07:00

ddr3_16bit

fpga: e31x: Fix DRAM traffic gen IP name

2022-03-23 08:55:36 -05:00

e31x_ps_bd

e31x: Swap out liberio for internal Ethernet

2020-07-16 10:00:12 -05:00

fifo_4k_2clk

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

fifo_short_2clk

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

Makefile.inc

fpga: e31x: Add DRAM support

2022-02-10 18:13:44 -07:00