Wade Fife d6849765ec fpga: sim: chdr_stream_endpoint_tb improvements ...

- Adds test coverage for stream command and status packets
- Cleans up report output during simulation
- Stops clocks at the end of simulation, so chdr_stream_endpoint_tb can
  be run directly instead of just chdr_stream_endpoint_all_tb


Original-commit: 97cb396297828f57bba455a275966c58f1abce6e

2020-08-31 08:16:43 -05:00

..

chdr_stream_endpoint_all_tb.sv

fpga: sim: chdr_stream_endpoint_tb improvements

2020-08-31 08:16:43 -05:00

chdr_stream_endpoint_tb.sv

fpga: sim: chdr_stream_endpoint_tb improvements

2020-08-31 08:16:43 -05:00

lossy_xport_model.v

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

Makefile

fpga: rfnoc: Add support for 512-bit CHDR widths

2020-06-18 09:09:34 -05:00