37 lines
1.5 KiB
Systemverilog
37 lines
1.5 KiB
Systemverilog
//
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// Copyright 2021 Ettus Research, A National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: radio_dio_regmap_utils.vh
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// Description:
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// The constants in this file are autogenerated by XmlParse.
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//===============================================================================
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// A numerically ordered list of registers and their HDL source files
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//===============================================================================
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// RADIO_GPIO_ATR_REGS : 0x0 (x4xx_core_common.v)
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// DIO_SOURCE_CONTROL : 0x1000 (x4xx_core_common.v)
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// DIGITAL_IFC_REGS : 0x2000 (x4xx_core_common.v)
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//===============================================================================
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// RegTypes
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//===============================================================================
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//===============================================================================
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// Register Group DIO_SOURCES
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//===============================================================================
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// RADIO_GPIO_ATR_REGS Window (from x4xx_core_common.v)
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localparam RADIO_GPIO_ATR_REGS = 'h0; // Window Offset
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localparam RADIO_GPIO_ATR_REGS_SIZE = 'h1000; // size in bytes
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// DIO_SOURCE_CONTROL Window (from x4xx_core_common.v)
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localparam DIO_SOURCE_CONTROL = 'h1000; // Window Offset
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localparam DIO_SOURCE_CONTROL_SIZE = 'h1000; // size in bytes
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// DIGITAL_IFC_REGS Window (from x4xx_core_common.v)
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localparam DIGITAL_IFC_REGS = 'h2000; // Window Offset
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localparam DIGITAL_IFC_REGS_SIZE = 'h1000; // size in bytes
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