Martin Braun 6ef3795e42 fpga: Align build process for all targets ...

- All RFNoC capable targets now require rfnoc_image_builder to be built
- `make help` is updated for all targets to provide more useful and
  up-to-date information
- The FPGA manual is also updated
- All checked-in build artifacts are now removed from git
- axi_ram_fifo.yml is updated to provide include path information
  (required for building N3xx BIST images, which use this)


Original-commit: 28b994406d4c9547b1e2add62781b6a8162fdb74

2024-06-11 10:20:08 +02:00

..

coregen_dsp

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

dboards

fpga: n3xx: Add CE clock

2023-10-18 22:23:55 -05:00

doc

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

dts

fpga: n320: Add BIST (AA) image files

2020-07-31 14:32:54 -05:00

ip

fpga: Use AR76780 patch for fir_compiler

2022-08-25 13:55:30 -05:00

sim

fpga: n3xx: Upgrade to Vivado 2021.1

2022-08-25 13:55:30 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build_n3xx.tcl

fpga: Add incremental to strategies for e3xx, n3xx, x3xx

2024-03-14 16:35:11 -05:00

dev_config.json

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

Makefile

fpga: Align build process for all targets

2024-06-11 10:20:08 +02:00

Makefile.n3xx.inc

fpga: Align build process for all targets

2024-06-11 10:20:08 +02:00

mb_clocks.xdc

fpga: n3xx: Add CE clock

2023-10-18 22:23:55 -05:00

mb_pins.xdc

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

mb_timing.xdc

fpga: n3xx: Fix async clocks relationship

2022-08-25 13:55:30 -05:00

n3xx_clocking.v

n3xx: Add comments on clock_source=external,time_source=gpsdo

2024-02-21 06:40:57 -06:00

n3xx_core.v

fpga: n3xx: Add CE clock

2023-10-18 22:23:55 -05:00

n3xx_db_fe_core.v

fpga: Update copyright

2023-01-19 15:55:56 -08:00

n3xx_mgt_channel_wrapper.v

fpga: n3xx: Cleanup MTU parameters

2022-09-01 14:41:55 -05:00

n3xx_mgt_io_core.v

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

n3xx_mgt_wrapper.v

fpga: n3xx: Cleanup MTU parameters

2022-09-01 14:41:55 -05:00

n3xx_serial_dac_arb.vhd

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

n3xx_serial_dac.vhd

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

n3xx_wr_top.vhd

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

n3xx_wr.xdc

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

n300_bist_rfnoc_image_core.yml

fpga: Align build process for all targets

2024-06-11 10:20:08 +02:00

n300_rfnoc_image_core.yml

fpga: Align build process for all targets

2024-06-11 10:20:08 +02:00

n310_1ge.xdc

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

n310_10ge.xdc

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

n310_aurora.xdc

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

n310_bist_rfnoc_image_core.yml

fpga: Align build process for all targets

2024-06-11 10:20:08 +02:00

n310_dram.xdc

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

n310_rfnoc_image_core.yml

fpga: Align build process for all targets

2024-06-11 10:20:08 +02:00

n320_bist_rfnoc_image_core.yml

fpga: Align build process for all targets

2024-06-11 10:20:08 +02:00

n320_rfnoc_image_core.yml

fpga: Align build process for all targets

2024-06-11 10:20:08 +02:00

setupenv.sh

fpga: Use AR76780 patch for fir_compiler

2022-08-25 13:55:30 -05:00

WrapBufg.vhd

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00