671 lines
29 KiB
Verilog
671 lines
29 KiB
Verilog
//
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// Copyright 2021 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: x4xx_core_common
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//
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// Description:
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//
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// This module contains the common core infrastructure for RFNoC, such as the
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// motherboard registers and timekeeper, as well as distribution of the
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// CtrlPort buses from each radio block.
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//
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// Parameters:
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//
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// CHDR_CLK_RATE : Rate of rfnoc_chdr_clk in Hz
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// CHDR_W : CHDR protocol width
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// RFNOC_PROTOVER : RFNoC protocol version (major in most-significant byte,
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// Minor is least significant byte)
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// NUM_DBOARDS : Number of daughter boards to support
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// PCIE_PRESENT : Indicates if PCIe is present in this image
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//
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`default_nettype none
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module x4xx_core_common #(
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parameter CHDR_CLK_RATE = 200000000,
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parameter CHDR_W = 64,
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parameter RFNOC_PROTOVER = {8'd1, 8'd0},
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parameter NUM_DBOARDS = 2,
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parameter PCIE_PRESENT = 0
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) (
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// Clocks and resets
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input wire radio_clk,
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input wire radio_rst,
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input wire rfnoc_chdr_clk,
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input wire rfnoc_chdr_rst,
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input wire rfnoc_ctrl_clk,
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input wire rfnoc_ctrl_rst,
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// Ctrlport master interface from AXI
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input wire ctrlport_rst,
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input wire ctrlport_clk,
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input wire s_ctrlport_req_wr,
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input wire s_ctrlport_req_rd,
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input wire [19:0] s_ctrlport_req_addr,
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input wire [ 9:0] s_ctrlport_req_portid,
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input wire [15:0] s_ctrlport_req_rem_epid,
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input wire [ 9:0] s_ctrlport_req_rem_portid,
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input wire [31:0] s_ctrlport_req_data,
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input wire [ 3:0] s_ctrlport_req_byte_en,
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input wire s_ctrlport_req_has_time,
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input wire [63:0] s_ctrlport_req_time,
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output wire s_ctrlport_resp_ack,
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output wire [ 1:0] s_ctrlport_resp_status,
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output wire [31:0] s_ctrlport_resp_data,
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// PPS (top-level inputs)
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input wire pps_radioclk,
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// PPS and clock control (Domain: rfnoc_ctrl_clk)
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output wire [ 1:0] pps_select,
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output wire [ 1:0] trig_io_select,
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output wire pll_sync_trigger,
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output wire [ 7:0] pll_sync_delay,
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input wire pll_sync_done,
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output wire [ 7:0] pps_brc_delay,
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output wire [25:0] pps_prc_delay,
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output wire [ 1:0] prc_rc_divider,
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output wire pps_rc_enabled,
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// Timekeeper (Domain: radio_clk)
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input wire [ 7:0] radio_spc,
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output wire [63:0] radio_time,
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input wire sample_rx_stb,
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input wire [ 3:0] time_ignore_bits,
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// GPIO to DIO board (Domain: radio_clk)
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output wire [11:0] gpio_en_a,
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output wire [11:0] gpio_en_b,
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// GPIO to DIO board (async)
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input wire [11:0] gpio_in_a,
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input wire [11:0] gpio_in_b,
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output wire [11:0] gpio_out_a,
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output wire [11:0] gpio_out_b,
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// GPIO to application (Domain: async)
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output wire [11:0] gpio_in_fabric_a,
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output wire [11:0] gpio_in_fabric_b,
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input wire [11:0] gpio_out_fabric_a,
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input wire [11:0] gpio_out_fabric_b,
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// CtrlPort Slave (from RFNoC Radio Blocks; Domain: radio_clk)
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input wire [ 1*NUM_DBOARDS-1:0] s_radio_ctrlport_req_wr,
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input wire [ 1*NUM_DBOARDS-1:0] s_radio_ctrlport_req_rd,
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input wire [ 20*NUM_DBOARDS-1:0] s_radio_ctrlport_req_addr,
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input wire [ 32*NUM_DBOARDS-1:0] s_radio_ctrlport_req_data,
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input wire [ 4*NUM_DBOARDS-1:0] s_radio_ctrlport_req_byte_en,
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input wire [ 1*NUM_DBOARDS-1:0] s_radio_ctrlport_req_has_time,
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input wire [ 64*NUM_DBOARDS-1:0] s_radio_ctrlport_req_time,
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output wire [ 1*NUM_DBOARDS-1:0] s_radio_ctrlport_resp_ack,
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output wire [ 2*NUM_DBOARDS-1:0] s_radio_ctrlport_resp_status,
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output wire [ 32*NUM_DBOARDS-1:0] s_radio_ctrlport_resp_data,
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// CtrlPort Master (to Daughter Boards, Domain: radio_clk)
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output wire [ 1*NUM_DBOARDS-1:0] m_radio_ctrlport_req_wr,
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output wire [ 1*NUM_DBOARDS-1:0] m_radio_ctrlport_req_rd,
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output wire [ 20*NUM_DBOARDS-1:0] m_radio_ctrlport_req_addr,
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output wire [ 32*NUM_DBOARDS-1:0] m_radio_ctrlport_req_data,
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output wire [ 4*NUM_DBOARDS-1:0] m_radio_ctrlport_req_byte_en,
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output wire [ 1*NUM_DBOARDS-1:0] m_radio_ctrlport_req_has_time,
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output wire [ 64*NUM_DBOARDS-1:0] m_radio_ctrlport_req_time,
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input wire [ 1*NUM_DBOARDS-1:0] m_radio_ctrlport_resp_ack,
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input wire [ 2*NUM_DBOARDS-1:0] m_radio_ctrlport_resp_status,
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input wire [ 32*NUM_DBOARDS-1:0] m_radio_ctrlport_resp_data,
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// RF Reset Control
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output wire start_nco_reset,
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input wire nco_reset_done,
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output wire adc_reset_pulse,
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output wire dac_reset_pulse,
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// Misc (Domain: rfnoc_ctrl_clk)
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input wire [31:0] qsfp_port_0_0_info,
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input wire [31:0] qsfp_port_0_1_info,
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input wire [31:0] qsfp_port_0_2_info,
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input wire [31:0] qsfp_port_0_3_info,
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input wire [31:0] qsfp_port_1_0_info,
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input wire [31:0] qsfp_port_1_1_info,
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input wire [31:0] qsfp_port_1_2_info,
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input wire [31:0] qsfp_port_1_3_info,
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output wire [15:0] device_id,
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output wire mfg_test_en_fabric_clk,
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output wire mfg_test_en_gty_rcv_clk,
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input wire fpga_aux_ref,
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// Version (Constant)
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// Each component consists of a 96-bit vector (refer to versioning_utils.vh)
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input wire [64*96-1:0] version_info
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);
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`include "regmap/radio_ctrlport_regmap_utils.vh"
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`include "../../lib/rfnoc/core/ctrlport.vh"
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`include "regmap/core_regs_regmap_utils.vh"
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//---------------------------------------------------------------------------
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// AXI4-Lite to ctrlport
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//---------------------------------------------------------------------------
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// Ctrlport master interface (domain: rfnoc_ctrl_clk)
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wire m_req_wr;
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wire m_req_rd;
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wire [CTRLPORT_ADDR_W-1:0] m_req_addr;
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wire [CTRLPORT_DATA_W-1:0] m_req_data;
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wire m_resp_ack;
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wire [ CTRLPORT_STS_W-1:0] m_resp_status;
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wire [CTRLPORT_DATA_W-1:0] m_resp_data;
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// Split ctrlport for multiple endpoints (domain: rfnoc_ctrl_clk)
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wire timekeeper_req_wr, versioning_req_wr, global_regs_req_wr, dio_req_wr;
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wire timekeeper_req_rd, versioning_req_rd, global_regs_req_rd, dio_req_rd;
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wire [CTRLPORT_ADDR_W-1:0] timekeeper_req_addr, versioning_req_addr, global_regs_req_addr, dio_req_addr;
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wire [CTRLPORT_DATA_W-1:0] timekeeper_req_data, versioning_req_data, global_regs_req_data, dio_req_data;
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wire timekeeper_resp_ack, versioning_resp_ack, global_regs_resp_ack, dio_resp_ack;
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wire [ CTRLPORT_STS_W-1:0] timekeeper_resp_status, versioning_resp_status, global_regs_resp_status, dio_resp_status;
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wire [CTRLPORT_DATA_W-1:0] timekeeper_resp_data, versioning_resp_data, global_regs_resp_data, dio_resp_data;
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ctrlport_clk_cross ctrlport_clk_cross_i (
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.rst (ctrlport_rst),
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.s_ctrlport_clk (ctrlport_clk),
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.s_ctrlport_req_wr (s_ctrlport_req_wr),
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.s_ctrlport_req_rd (s_ctrlport_req_rd),
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.s_ctrlport_req_addr (s_ctrlport_req_addr),
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.s_ctrlport_req_portid (s_ctrlport_req_portid),
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.s_ctrlport_req_rem_epid (s_ctrlport_req_rem_epid),
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.s_ctrlport_req_rem_portid (s_ctrlport_req_rem_portid),
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.s_ctrlport_req_data (s_ctrlport_req_data),
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.s_ctrlport_req_byte_en (s_ctrlport_req_byte_en),
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.s_ctrlport_req_has_time (s_ctrlport_req_has_time),
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.s_ctrlport_req_time (s_ctrlport_req_time),
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.s_ctrlport_resp_ack (s_ctrlport_resp_ack),
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.s_ctrlport_resp_status (s_ctrlport_resp_status),
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.s_ctrlport_resp_data (s_ctrlport_resp_data),
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.m_ctrlport_clk (rfnoc_ctrl_clk),
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.m_ctrlport_req_wr (m_req_wr),
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.m_ctrlport_req_rd (m_req_rd),
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.m_ctrlport_req_addr (m_req_addr),
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.m_ctrlport_req_portid (),
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.m_ctrlport_req_rem_epid (),
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.m_ctrlport_req_rem_portid (),
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.m_ctrlport_req_data (m_req_data),
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.m_ctrlport_req_byte_en (),
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.m_ctrlport_req_has_time (),
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.m_ctrlport_req_time (),
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.m_ctrlport_resp_ack (m_resp_ack),
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.m_ctrlport_resp_status (m_resp_status),
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.m_ctrlport_resp_data (m_resp_data)
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);
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ctrlport_splitter #(
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.NUM_SLAVES (4)
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) ctrlport_splitter_i (
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.ctrlport_clk (rfnoc_ctrl_clk),
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.ctrlport_rst (rfnoc_ctrl_rst),
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.s_ctrlport_req_wr (m_req_wr),
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.s_ctrlport_req_rd (m_req_rd),
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.s_ctrlport_req_addr (m_req_addr),
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.s_ctrlport_req_data (m_req_data),
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.s_ctrlport_req_byte_en (4'hF),
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.s_ctrlport_req_has_time (1'b0),
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.s_ctrlport_req_time (64'h0),
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.s_ctrlport_resp_ack (m_resp_ack),
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.s_ctrlport_resp_status (m_resp_status),
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.s_ctrlport_resp_data (m_resp_data),
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.m_ctrlport_req_wr ({timekeeper_req_wr, versioning_req_wr, global_regs_req_wr, dio_req_wr}),
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.m_ctrlport_req_rd ({timekeeper_req_rd, versioning_req_rd, global_regs_req_rd, dio_req_rd}),
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.m_ctrlport_req_addr ({timekeeper_req_addr, versioning_req_addr, global_regs_req_addr, dio_req_addr}),
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.m_ctrlport_req_data ({timekeeper_req_data, versioning_req_data, global_regs_req_data, dio_req_data}),
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.m_ctrlport_req_byte_en (),
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.m_ctrlport_req_has_time (),
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.m_ctrlport_req_time (),
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.m_ctrlport_resp_ack ({timekeeper_resp_ack, versioning_resp_ack, global_regs_resp_ack, dio_resp_ack}),
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.m_ctrlport_resp_status ({timekeeper_resp_status, versioning_resp_status, global_regs_resp_status, dio_resp_status}),
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.m_ctrlport_resp_data ({timekeeper_resp_data, versioning_resp_data, global_regs_resp_data, dio_resp_data})
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);
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//--------------------------------------------------------------------
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// Global Registers
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// -------------------------------------------------------------------
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localparam NUM_TIMEKEEPERS = 1;
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x4xx_global_regs #(
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.REG_BASE (GLOBAL_REGS),
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.REG_SIZE (GLOBAL_REGS_SIZE),
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.CHDR_CLK_RATE (CHDR_CLK_RATE),
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.CHDR_W (CHDR_W),
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.RFNOC_PROTOVER (RFNOC_PROTOVER),
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.NUM_TIMEKEEPERS (NUM_TIMEKEEPERS),
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.PCIE_PRESENT (PCIE_PRESENT)
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) x4xx_global_regs_i (
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.s_ctrlport_clk (rfnoc_ctrl_clk),
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.s_ctrlport_rst (rfnoc_ctrl_rst),
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.s_ctrlport_req_wr (global_regs_req_wr),
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.s_ctrlport_req_rd (global_regs_req_rd),
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.s_ctrlport_req_addr (global_regs_req_addr),
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.s_ctrlport_req_data (global_regs_req_data),
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.s_ctrlport_resp_ack (global_regs_resp_ack),
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.s_ctrlport_resp_status (global_regs_resp_status),
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.s_ctrlport_resp_data (global_regs_resp_data),
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.rfnoc_chdr_clk (rfnoc_chdr_clk),
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.rfnoc_chdr_rst (rfnoc_chdr_rst),
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.pps_select (pps_select),
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.trig_io_select (trig_io_select),
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.pll_sync_trigger (pll_sync_trigger),
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.pll_sync_delay (pll_sync_delay),
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.pll_sync_done (pll_sync_done),
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.pps_brc_delay (pps_brc_delay),
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.pps_prc_delay (pps_prc_delay),
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.prc_rc_divider (prc_rc_divider),
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.pps_rc_enabled (pps_rc_enabled),
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.qsfp_port_0_0_info (qsfp_port_0_0_info),
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.qsfp_port_0_1_info (qsfp_port_0_1_info),
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.qsfp_port_0_2_info (qsfp_port_0_2_info),
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.qsfp_port_0_3_info (qsfp_port_0_3_info),
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.qsfp_port_1_0_info (qsfp_port_1_0_info),
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.qsfp_port_1_1_info (qsfp_port_1_1_info),
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.qsfp_port_1_2_info (qsfp_port_1_2_info),
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.qsfp_port_1_3_info (qsfp_port_1_3_info),
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.mfg_test_en_fabric_clk (mfg_test_en_fabric_clk),
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.mfg_test_en_gty_rcv_clk (mfg_test_en_gty_rcv_clk),
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.fpga_aux_ref (fpga_aux_ref),
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.device_id (device_id)
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);
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//--------------------------------------------------------------------
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// Version Registers
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// -------------------------------------------------------------------
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x4xx_versioning_regs #(
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.REG_BASE (VERSIONING_REGS)
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) x4xx_versioning_regs_i (
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.s_ctrlport_clk (rfnoc_ctrl_clk),
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.s_ctrlport_rst (rfnoc_ctrl_rst),
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.s_ctrlport_req_wr (versioning_req_wr),
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.s_ctrlport_req_rd (versioning_req_rd),
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.s_ctrlport_req_addr (versioning_req_addr),
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.s_ctrlport_req_data (versioning_req_data),
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.s_ctrlport_resp_ack (versioning_resp_ack),
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.s_ctrlport_resp_status (versioning_resp_status),
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.s_ctrlport_resp_data (versioning_resp_data),
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.version_info (version_info)
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);
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//---------------------------------------------------------------------------
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// Timekeeper
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//---------------------------------------------------------------------------
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assign timekeeper_resp_status = CTRL_STS_OKAY;
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timekeeper #(
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.BASE_ADDR (TIMEKEEPER),
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.TIME_INCREMENT (0)
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) timekeeper_i (
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.tb_clk (radio_clk),
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.tb_rst (radio_rst),
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.s_ctrlport_clk (rfnoc_ctrl_clk),
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.s_ctrlport_req_wr (timekeeper_req_wr),
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.s_ctrlport_req_rd (timekeeper_req_rd),
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.s_ctrlport_req_addr (timekeeper_req_addr),
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.s_ctrlport_req_data (timekeeper_req_data),
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.s_ctrlport_resp_ack (timekeeper_resp_ack),
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.s_ctrlport_resp_data (timekeeper_resp_data),
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.time_increment (radio_spc),
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.sample_rx_stb (sample_rx_stb),
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.pps (pps_radioclk),
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.tb_timestamp (radio_time),
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.tb_timestamp_last_pps (),
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.tb_period_ns_q32 ()
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);
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//-----------------------------------------------------------------------
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// Radio CtrlPort Splitter
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//-----------------------------------------------------------------------
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wire [ 1*NUM_DBOARDS-1:0] rf_ctrlport_req_wr;
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wire [ 1*NUM_DBOARDS-1:0] rf_ctrlport_req_rd;
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wire [ 20*NUM_DBOARDS-1:0] rf_ctrlport_req_addr;
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wire [ 32*NUM_DBOARDS-1:0] rf_ctrlport_req_data;
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wire [ 4*NUM_DBOARDS-1:0] rf_ctrlport_req_byte_en;
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wire [ 1*NUM_DBOARDS-1:0] rf_ctrlport_req_has_time;
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wire [ 64*NUM_DBOARDS-1:0] rf_ctrlport_req_time;
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wire [ 1*NUM_DBOARDS-1:0] rf_ctrlport_resp_ack;
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wire [ 2*NUM_DBOARDS-1:0] rf_ctrlport_resp_status;
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wire [ 32*NUM_DBOARDS-1:0] rf_ctrlport_resp_data;
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wire [ 1*NUM_DBOARDS-1:0] dio_radio_ctrlport_req_wr;
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wire [ 1*NUM_DBOARDS-1:0] dio_radio_ctrlport_req_rd;
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wire [ 20*NUM_DBOARDS-1:0] dio_radio_ctrlport_req_addr;
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wire [ 32*NUM_DBOARDS-1:0] dio_radio_ctrlport_req_data;
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wire [ 4*NUM_DBOARDS-1:0] dio_radio_ctrlport_req_byte_en;
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wire [ 1*NUM_DBOARDS-1:0] dio_radio_ctrlport_req_has_time;
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wire [ 64*NUM_DBOARDS-1:0] dio_radio_ctrlport_req_time;
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wire [ 1*NUM_DBOARDS-1:0] dio_radio_ctrlport_resp_ack;
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wire [ 2*NUM_DBOARDS-1:0] dio_radio_ctrlport_resp_status;
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wire [ 32*NUM_DBOARDS-1:0] dio_radio_ctrlport_resp_data;
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genvar db;
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generate
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for (db = 0; db < NUM_DBOARDS; db = db+1) begin : gen_radio_ctrlport
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//-----------------------------------------------------------------------
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// CtrlPort Splitter
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//-----------------------------------------------------------------------
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// This section takes the CtrlPort master from each radio block and splits it
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// into a CtrlPort bus for the associated daughter(m_radio_ctrlport_*), the
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// RFDC timing control (rf_ctrlport_*) and DIO control(dio_radio_ctrlport_*).
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localparam [31:0] DIO_WINDOW_SIZE_W = $clog2(DIO_WINDOW_SIZE);
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localparam [31:0] RFDC_TIMING_WINDOW_SIZE_W = $clog2(RFDC_TIMING_WINDOW_SIZE);
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localparam [31:0] DB_WINDOW_SIZE_W = $clog2(DB_WINDOW_SIZE);
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ctrlport_decoder_param #(
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.NUM_SLAVES (3),
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.PORT_BASE ({ DIO_WINDOW[19:0], RFDC_TIMING_WINDOW[19:0], DB_WINDOW[19:0] }),
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|
.PORT_ADDR_W ({ DIO_WINDOW_SIZE_W, RFDC_TIMING_WINDOW_SIZE_W, DB_WINDOW_SIZE_W })
|
|
) ctrlport_decoder_param_i (
|
|
.ctrlport_clk (radio_clk),
|
|
.ctrlport_rst (radio_rst),
|
|
.s_ctrlport_req_wr (s_radio_ctrlport_req_wr [ 1*db+: 1]),
|
|
.s_ctrlport_req_rd (s_radio_ctrlport_req_rd [ 1*db+: 1]),
|
|
.s_ctrlport_req_addr (s_radio_ctrlport_req_addr [20*db+:20]),
|
|
.s_ctrlport_req_data (s_radio_ctrlport_req_data [32*db+:32]),
|
|
.s_ctrlport_req_byte_en (s_radio_ctrlport_req_byte_en [ 4*db+: 4]),
|
|
.s_ctrlport_req_has_time (s_radio_ctrlport_req_has_time [ 1*db+: 1]),
|
|
.s_ctrlport_req_time (s_radio_ctrlport_req_time [64*db+:64]),
|
|
.s_ctrlport_resp_ack (s_radio_ctrlport_resp_ack [ 1*db+: 1]),
|
|
.s_ctrlport_resp_status (s_radio_ctrlport_resp_status [ 2*db+: 2]),
|
|
.s_ctrlport_resp_data (s_radio_ctrlport_resp_data [32*db+:32]),
|
|
.m_ctrlport_req_wr ({ dio_radio_ctrlport_req_wr [ 1*db+: 1], rf_ctrlport_req_wr [ 1*db+: 1], m_radio_ctrlport_req_wr [ 1*db+: 1] }),
|
|
.m_ctrlport_req_rd ({ dio_radio_ctrlport_req_rd [ 1*db+: 1], rf_ctrlport_req_rd [ 1*db+: 1], m_radio_ctrlport_req_rd [ 1*db+: 1] }),
|
|
.m_ctrlport_req_addr ({ dio_radio_ctrlport_req_addr [20*db+:20], rf_ctrlport_req_addr [20*db+:20], m_radio_ctrlport_req_addr [20*db+:20] }),
|
|
.m_ctrlport_req_data ({ dio_radio_ctrlport_req_data [32*db+:32], rf_ctrlport_req_data [32*db+:32], m_radio_ctrlport_req_data [32*db+:32] }),
|
|
.m_ctrlport_req_byte_en ({ dio_radio_ctrlport_req_byte_en [ 4*db+: 4], rf_ctrlport_req_byte_en [ 4*db+: 4], m_radio_ctrlport_req_byte_en [ 4*db+: 4] }),
|
|
.m_ctrlport_req_has_time ({ dio_radio_ctrlport_req_has_time [ 1*db+: 1], rf_ctrlport_req_has_time [ 1*db+: 1], m_radio_ctrlport_req_has_time [ 1*db+: 1] }),
|
|
.m_ctrlport_req_time ({ dio_radio_ctrlport_req_time [64*db+:64], rf_ctrlport_req_time [64*db+:64], m_radio_ctrlport_req_time [64*db+:64] }),
|
|
.m_ctrlport_resp_ack ({ dio_radio_ctrlport_resp_ack [ 1*db+: 1], rf_ctrlport_resp_ack [ 1*db+: 1], m_radio_ctrlport_resp_ack [ 1*db+: 1] }),
|
|
.m_ctrlport_resp_status ({ dio_radio_ctrlport_resp_status [ 2*db+: 2], rf_ctrlport_resp_status [ 2*db+: 2], m_radio_ctrlport_resp_status [ 2*db+: 2] }),
|
|
.m_ctrlport_resp_data ({ dio_radio_ctrlport_resp_data [32*db+:32], rf_ctrlport_resp_data [32*db+:32], m_radio_ctrlport_resp_data [32*db+:32] })
|
|
);
|
|
|
|
end
|
|
endgenerate
|
|
|
|
|
|
//-------------------------------------------------------------------------
|
|
// RF Timing Reset Control
|
|
//-------------------------------------------------------------------------
|
|
|
|
rfdc_timing_control #(
|
|
.NUM_DBOARDS (NUM_DBOARDS)
|
|
) rfdc_timing_control_i (
|
|
.clk (radio_clk),
|
|
.rst (radio_rst),
|
|
.time_now (radio_time),
|
|
.time_now_stb (sample_rx_stb),
|
|
.time_ignore_bits (time_ignore_bits),
|
|
.s_ctrlport_req_wr (rf_ctrlport_req_wr),
|
|
.s_ctrlport_req_rd (rf_ctrlport_req_rd),
|
|
.s_ctrlport_req_addr (rf_ctrlport_req_addr),
|
|
.s_ctrlport_req_data (rf_ctrlport_req_data),
|
|
.s_ctrlport_req_byte_en (rf_ctrlport_req_byte_en),
|
|
.s_ctrlport_req_has_time (rf_ctrlport_req_has_time),
|
|
.s_ctrlport_req_time (rf_ctrlport_req_time),
|
|
.s_ctrlport_resp_ack (rf_ctrlport_resp_ack),
|
|
.s_ctrlport_resp_status (rf_ctrlport_resp_status),
|
|
.s_ctrlport_resp_data (rf_ctrlport_resp_data),
|
|
.start_nco_reset (start_nco_reset),
|
|
.nco_reset_done (nco_reset_done),
|
|
.adc_reset_pulse (adc_reset_pulse),
|
|
.dac_reset_pulse (dac_reset_pulse)
|
|
);
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
// DIO
|
|
//---------------------------------------------------------------------------
|
|
//
|
|
// DIO lines may be controlled via 3 different ctrlport interfaces.
|
|
// The diagram below shows how the different ctrlport interfaces are
|
|
// conditioned and combined.
|
|
//
|
|
// ________________
|
|
// ps ctrlport | |
|
|
// ----------------------| CLK crossing |-------+
|
|
// |(rfnoc_ctrl_clk)| |
|
|
// |________________| |
|
|
// radio 0 dio_ctrlport | _____________
|
|
// -------------------------------------------+ +----| |
|
|
// | | Ctrlport |
|
|
// +--------| combiner |---- x4xx_dio
|
|
// radio 1 dio_ctrlport | |
|
|
// ----------------------------------------------------|_____________|
|
|
// (radio_clk)
|
|
//
|
|
//
|
|
|
|
// MPM ctrlport signals to convert to radio_clk domain
|
|
wire mpm_dio_req_wr;
|
|
wire mpm_dio_req_rd;
|
|
wire [19:0] mpm_dio_req_addr;
|
|
wire [31:0] mpm_dio_req_data;
|
|
wire mpm_dio_resp_ack;
|
|
wire [ 1:0] mpm_dio_resp_status;
|
|
wire [31:0] mpm_dio_resp_data;
|
|
|
|
ctrlport_clk_cross ctrlport_clk_cross_dio (
|
|
.rst (rfnoc_ctrl_rst),
|
|
.s_ctrlport_clk (rfnoc_ctrl_clk),
|
|
.s_ctrlport_req_wr (dio_req_wr),
|
|
.s_ctrlport_req_rd (dio_req_rd),
|
|
.s_ctrlport_req_addr (dio_req_addr),
|
|
.s_ctrlport_req_portid (10'b0),
|
|
.s_ctrlport_req_rem_epid (16'b0),
|
|
.s_ctrlport_req_rem_portid (10'b0),
|
|
.s_ctrlport_req_data (dio_req_data),
|
|
.s_ctrlport_req_byte_en (4'hF),
|
|
.s_ctrlport_req_has_time (1'b0),
|
|
.s_ctrlport_req_time (64'b0),
|
|
.s_ctrlport_resp_ack (dio_resp_ack),
|
|
.s_ctrlport_resp_status (dio_resp_status),
|
|
.s_ctrlport_resp_data (dio_resp_data),
|
|
.m_ctrlport_clk (radio_clk),
|
|
.m_ctrlport_req_wr (mpm_dio_req_wr),
|
|
.m_ctrlport_req_rd (mpm_dio_req_rd),
|
|
.m_ctrlport_req_addr (mpm_dio_req_addr),
|
|
.m_ctrlport_req_portid (),
|
|
.m_ctrlport_req_rem_epid (),
|
|
.m_ctrlport_req_rem_portid (),
|
|
.m_ctrlport_req_data (mpm_dio_req_data),
|
|
.m_ctrlport_req_byte_en (),
|
|
.m_ctrlport_req_has_time (),
|
|
.m_ctrlport_req_time (),
|
|
.m_ctrlport_resp_ack (mpm_dio_resp_ack),
|
|
.m_ctrlport_resp_status (mpm_dio_resp_status),
|
|
.m_ctrlport_resp_data (mpm_dio_resp_data)
|
|
);
|
|
|
|
// Since the PS ctrlport services other register endpoints
|
|
// outside the DIO register space, none of which are addressed
|
|
// through the ctrlport signals in the radio_clk domain.
|
|
// For this reason, ctrlport transactions not intended for the
|
|
// DIO register space will hang the bus if pushed into
|
|
// the ctrlport_combiner. For this reason, transactions out
|
|
// of said space will be filtered out from this clock crossed
|
|
// instance of the PS ctrlport.
|
|
|
|
// Windowed ctrlport signals
|
|
wire windowed_mpm_dio_req_wr;
|
|
wire windowed_mpm_dio_req_rd;
|
|
wire [19:0] windowed_mpm_dio_req_addr;
|
|
wire [31:0] windowed_mpm_dio_req_data;
|
|
wire windowed_mpm_dio_resp_ack;
|
|
wire [ 1:0] windowed_mpm_dio_resp_status;
|
|
wire [31:0] windowed_mpm_dio_resp_data;
|
|
|
|
ctrlport_window #(
|
|
.BASE_ADDRESS (DIO),
|
|
.WINDOW_SIZE (DIO_SIZE)
|
|
) ctrlport_window_dio (
|
|
.s_ctrlport_req_wr (mpm_dio_req_wr),
|
|
.s_ctrlport_req_rd (mpm_dio_req_rd),
|
|
.s_ctrlport_req_addr (mpm_dio_req_addr),
|
|
.s_ctrlport_req_portid (10'b0),
|
|
.s_ctrlport_req_rem_epid (16'b0),
|
|
.s_ctrlport_req_rem_portid (10'b0),
|
|
.s_ctrlport_req_data (mpm_dio_req_data),
|
|
.s_ctrlport_req_byte_en (4'hF),
|
|
.s_ctrlport_req_has_time (1'b0),
|
|
.s_ctrlport_req_time (64'b0),
|
|
.s_ctrlport_resp_ack (mpm_dio_resp_ack),
|
|
.s_ctrlport_resp_status (mpm_dio_resp_status),
|
|
.s_ctrlport_resp_data (mpm_dio_resp_data),
|
|
.m_ctrlport_req_wr (windowed_mpm_dio_req_wr),
|
|
.m_ctrlport_req_rd (windowed_mpm_dio_req_rd),
|
|
.m_ctrlport_req_addr (windowed_mpm_dio_req_addr),
|
|
.m_ctrlport_req_portid (),
|
|
.m_ctrlport_req_rem_epid (),
|
|
.m_ctrlport_req_rem_portid (),
|
|
.m_ctrlport_req_data (windowed_mpm_dio_req_data),
|
|
.m_ctrlport_req_byte_en (),
|
|
.m_ctrlport_req_has_time (),
|
|
.m_ctrlport_req_time (),
|
|
.m_ctrlport_resp_ack (windowed_mpm_dio_resp_ack),
|
|
.m_ctrlport_resp_status (windowed_mpm_dio_resp_status),
|
|
.m_ctrlport_resp_data (windowed_mpm_dio_resp_data)
|
|
);
|
|
|
|
|
|
// Combined ctrlport signals
|
|
wire dio_ctrlport_req_wr;
|
|
wire dio_ctrlport_req_rd;
|
|
wire [19:0] dio_ctrlport_req_addr;
|
|
wire [31:0] dio_ctrlport_req_data;
|
|
wire dio_ctrlport_resp_ack;
|
|
wire [ 1:0] dio_ctrlport_resp_status;
|
|
wire [31:0] dio_ctrlport_resp_data;
|
|
|
|
// This combiner mixes the CtrlPort interfaces from each radio block with the
|
|
// filtered PS CtrlPort bus to allow these interfaces to interact with the
|
|
// DIO block.
|
|
ctrlport_combiner #(
|
|
.NUM_MASTERS (NUM_DBOARDS + 1),
|
|
.PRIORITY (1)
|
|
) ctrlport_combiner_dio (
|
|
.ctrlport_clk (radio_clk),
|
|
.ctrlport_rst (radio_rst),
|
|
.s_ctrlport_req_wr ({dio_radio_ctrlport_req_wr, windowed_mpm_dio_req_wr}),
|
|
.s_ctrlport_req_rd ({dio_radio_ctrlport_req_rd, windowed_mpm_dio_req_rd}),
|
|
.s_ctrlport_req_addr ({dio_radio_ctrlport_req_addr, windowed_mpm_dio_req_addr}),
|
|
.s_ctrlport_req_portid ({(NUM_DBOARDS+1){10'b0}}),
|
|
.s_ctrlport_req_rem_epid ({(NUM_DBOARDS+1){16'b0}}),
|
|
.s_ctrlport_req_rem_portid ({(NUM_DBOARDS+1){10'b0}}),
|
|
.s_ctrlport_req_data ({dio_radio_ctrlport_req_data, windowed_mpm_dio_req_data}),
|
|
.s_ctrlport_req_byte_en ({(NUM_DBOARDS+1){4'hF}}),
|
|
.s_ctrlport_req_has_time ({(NUM_DBOARDS+1){1'b0}}),
|
|
.s_ctrlport_req_time ({(NUM_DBOARDS+1){64'b0}}),
|
|
.s_ctrlport_resp_ack ({dio_radio_ctrlport_resp_ack, windowed_mpm_dio_resp_ack}),
|
|
.s_ctrlport_resp_status ({dio_radio_ctrlport_resp_status, windowed_mpm_dio_resp_status}),
|
|
.s_ctrlport_resp_data ({dio_radio_ctrlport_resp_data, windowed_mpm_dio_resp_data}),
|
|
.m_ctrlport_req_wr (dio_ctrlport_req_wr),
|
|
.m_ctrlport_req_rd (dio_ctrlport_req_rd),
|
|
.m_ctrlport_req_addr (dio_ctrlport_req_addr),
|
|
.m_ctrlport_req_portid (),
|
|
.m_ctrlport_req_rem_epid (),
|
|
.m_ctrlport_req_rem_portid (),
|
|
.m_ctrlport_req_data (dio_ctrlport_req_data),
|
|
.m_ctrlport_req_byte_en (),
|
|
.m_ctrlport_req_has_time (),
|
|
.m_ctrlport_req_time (),
|
|
.m_ctrlport_resp_ack (dio_ctrlport_resp_ack),
|
|
.m_ctrlport_resp_status (dio_ctrlport_resp_status),
|
|
.m_ctrlport_resp_data (dio_ctrlport_resp_data)
|
|
);
|
|
|
|
x4xx_dio #(
|
|
.REG_BASE (DIO),
|
|
.REG_SIZE (DIO_SIZE)
|
|
) x4xx_dio_i (
|
|
.ctrlport_clk (radio_clk),
|
|
.ctrlport_rst (radio_rst),
|
|
.s_ctrlport_req_wr (dio_ctrlport_req_wr),
|
|
.s_ctrlport_req_rd (dio_ctrlport_req_rd),
|
|
.s_ctrlport_req_addr (dio_ctrlport_req_addr),
|
|
.s_ctrlport_req_data (dio_ctrlport_req_data),
|
|
.s_ctrlport_resp_ack (dio_ctrlport_resp_ack),
|
|
.s_ctrlport_resp_status (dio_ctrlport_resp_status),
|
|
.s_ctrlport_resp_data (dio_ctrlport_resp_data),
|
|
.gpio_in_a (gpio_in_a),
|
|
.gpio_in_b (gpio_in_b),
|
|
.gpio_out_a (gpio_out_a),
|
|
.gpio_out_b (gpio_out_b),
|
|
.gpio_en_a (gpio_en_a),
|
|
.gpio_en_b (gpio_en_b),
|
|
.gpio_in_fabric_a (gpio_in_fabric_a),
|
|
.gpio_in_fabric_b (gpio_in_fabric_b),
|
|
.gpio_out_fabric_a (gpio_out_fabric_a),
|
|
.gpio_out_fabric_b (gpio_out_fabric_b)
|
|
);
|
|
|
|
endmodule
|
|
|
|
|
|
`default_nettype wire
|
|
|
|
|
|
//XmlParse xml_on
|
|
//
|
|
//<regmap name="RADIO_CTRLPORT_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
|
|
// <group name="RADIO_CTRLPORT_WINDOWS">
|
|
// <info>Each radio's CtrlPort peripheral interface is divided into the
|
|
// following memory spaces. Note that the CtrlPort peripheral interface
|
|
// starts at offset 0x80000 in the RFNoC Radio block's register space.</info>
|
|
// <window name="DB_WINDOW" offset="0x00000" size="0x08000">
|
|
// <info>Daughterboard GPIO interface. Register access within this space
|
|
// is directed to the associated daughterboard CPLD.</info>
|
|
// </window>
|
|
// <window name="RFDC_TIMING_WINDOW" offset="0x08000" size="0x04000" targetregmap="RFDC_TIMING_REGMAP">
|
|
// <info>RFDC timing control interface.</info>
|
|
// </window>
|
|
// <window name="DIO_WINDOW" offset="0x0C000" size="0x04000" targetregmap="DIO_REGMAP">
|
|
// <info>DIO control interface</info>
|
|
// </window>
|
|
// </group>
|
|
//</regmap>
|
|
//
|
|
//<regmap name="CORE_REGS_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
|
|
// <info>
|
|
// This is the map for the registers that the CORE_REGS window has access to
|
|
// from the ARM_AXI_HPM0_FPD port.
|
|
//
|
|
// The registers contained here conform the mboard-regs node that MPM uses
|
|
// to manage general FPGA control/status calls, such as versioning,
|
|
// timekeeper, GPIO, etc.
|
|
// </info>
|
|
// <group name="CORE_REGS">
|
|
// <window name="GLOBAL_REGS" offset="0x0" size="0xC00" targetregmap="GLOBAL_REGS_REGMAP">
|
|
// <info>Window to access global registers in the FPGA.</info>
|
|
// </window>
|
|
// <window name="VERSIONING_REGS" offset="0xC00" size="0x400" targetregmap="VERSIONING_REGS_REGMAP">
|
|
// <info>Window to access versioning registers in the FPGA.</info>
|
|
// </window>
|
|
// <window name="TIMEKEEPER" offset="0x1000" size="0x20">
|
|
// <info>Window to access the timekeeper register map.</info>
|
|
// </window>
|
|
// <window name="DIO" offset="0x2000" size="0x20" targetregmap="DIO_REGMAP">
|
|
// <info>Window to access the DIO register map.</info>
|
|
// </window>
|
|
// </group>
|
|
//</regmap>
|
|
//XmlParse xml_off
|