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4eb12794231cca555b1ccc24704eb78922839ee9
b210-k7-fpga/lib/rfnoc
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Wade Fife 4eb1279423 fpga: lib: Enable TUSER in eth_ipv4_interface_wrapper 
This wrapper was using TUSER for the number of trailing bytes, but it
wasn't properly enabled, which could cause it to be ignored in some
cases.


Original-commit: e7ebe601163d01d157bc3de9c2652952932e4a1c
2025-03-03 09:02:29 -06:00
..
blocks
fpga: rfnoc: Fix DDC overflow issue
2025-02-26 22:09:04 -06:00
core
rfnoc: lib: introduce ctrl-port interface and BFM
2025-02-14 08:04:26 -06:00
crossbar
fpga: lib: Fix Vivado warnings
2023-06-09 09:01:04 -05:00
fosphor
rfnoc: Add RFNoC fosphor block
2020-04-14 16:37:43 -05:00
sim
Fix instances of sim preamble
2024-09-17 08:43:22 -05:00
transport_adapters
fpga: x400: add CMAC placement constraints
2025-01-17 13:56:29 +01:00
utils
rfnoc: lib: introduce ctrl-port interface and BFM
2025-02-14 08:04:26 -06:00
xport
fpga: lib: Add MTU parameter to eth_internal
2022-09-01 14:41:55 -05:00
xport_sv
fpga: lib: Enable TUSER in eth_ipv4_interface_wrapper
2025-03-03 09:02:29 -06:00
.gitignore
fpga: rfnoc: Remove deprecated files
2020-08-23 13:52:26 -05:00
addsub.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
addsub.vhd
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_async_stream.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_bit_reduce.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_clip_complex.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_clip_unsigned.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_clip.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_deserializer.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_drop_partial_packet.v
fpga: rfnoc: Add defaults for rate changing
2020-05-28 15:12:20 -05:00
axi_fir_filter_dec.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_fir_filter.v
fpga: rfnoc: reverse FIR filter coefficients to get embedded in DSPE48
2024-04-26 15:19:23 -05:00
axi_join.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_packer.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_pipe_join.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_pipe_mac.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_pipe.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_rate_change.v
fpga: rfnoc: Add defaults for rate changing
2020-05-28 15:12:20 -05:00
axi_repeat.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_round_and_clip_complex.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_round_and_clip.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_round_complex.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_round.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_serializer.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_sync.v
fpga: lib: Clean up and document lib files
2021-08-08 14:59:26 -05:00
axi_tag_time.v
fpga: lib: Clean up and document lib files
2021-08-08 14:59:26 -05:00
cadd.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
chdr_fifo_large.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
cic_decimate.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
cic_interpolate.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
cmul.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
complex_invert.v
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2020-01-28 09:35:36 -08:00
complex_to_mag_approx.v
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2020-01-28 09:35:36 -08:00
complex_to_magsq.v
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2020-01-28 09:35:36 -08:00
conj.v
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2020-01-28 09:35:36 -08:00
const_sreg.v
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2020-01-28 09:35:36 -08:00
const.v
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2020-01-28 09:35:36 -08:00
counter.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
cvita_hdr_decoder.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
cvita_hdr_encoder.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
cvita_hdr_modify.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
cvita_hdr_parser.v
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2020-01-28 09:35:36 -08:00
data_types.vh
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
datapath_gatekeeper.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ddc.v
fpga: rfnoc: Fix DDC overflow issue
2025-02-26 22:09:04 -06:00
dds_freq_tune_duc.v
fpga: lib: Fix Vivado warnings
2023-06-09 09:01:04 -05:00
dds_freq_tune.v
FPGA: Fix warnings in dds_freq_tune module
2023-01-19 10:05:27 -06:00
dds_timed.v
fpga: rfnoc: Fix EOB loss in DUC
2021-08-08 14:59:26 -05:00
dds_wrapper.v
fpga: rfnoc: Fix EOB loss in DUC
2021-08-08 14:59:26 -05:00
delay_fifo.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
delay_type2.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
delay_type3.v
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2020-01-28 09:35:36 -08:00
delay_type4.v
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2020-01-28 09:35:36 -08:00
duc.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
fft_shift.v
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2020-01-28 09:35:36 -08:00
file_sink.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
file_source.v
fpga: Fix errors found by linting with vsim
2020-03-23 08:23:51 -05:00
fir_filter_slice.v
fpga: rfnoc: reverse FIR filter coefficients to get embedded in DSPE48
2024-04-26 15:19:23 -05:00
join_complex.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
keep_one_in_n.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
Makefile.srcs
fpga: Remove noc_shell_regs.vh and sim_rfnoc_lib.svh
2022-01-25 14:09:15 -07:00
moving_sum.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
mult_add_rc.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
mult_add.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
mult_rc.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
mult.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
multiply.v
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2020-01-28 09:35:36 -08:00
noc_traffic_counter.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
null_source.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
periodic_framer.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
phase_accum.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ram_to_fifo.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
sine_tone.v
siggen: Fix direction of rotation
2021-10-27 07:56:09 -07:00
split_complex.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
split_stream_fifo.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
split_stream.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
vector_iir.v
fpga: rfnoc: Add Vector IIR RFNoC block
2020-05-19 14:22:55 -05:00