Wade Fife
776860727e
The asynchronous feedback loop on the err signal causes X to get stuck on the sum signal when simulating. This change adds a check for simulation only to force X to 0 so that unknown inputs get resolved once the inputs are known. Also added default values to the ports out and strobe_out, since having them uninitialized and without reset was causing simulation issues in other modules. The FPGA will initialize them to 0, so this change makes the code equivalent to real hardware behavior. Original-commit: b9f7af5807f73a5ac2612ea42ac2b65c26a3bff2
75 lines
1.6 KiB
Verilog
75 lines
1.6 KiB
Verilog
//
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// Copyright 2021 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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module round_sd #(
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parameter WIDTH_IN = 18,
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parameter WIDTH_OUT = 16,
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parameter DISABLE_SD = 0
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) (
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input clk,
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input reset,
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input [ WIDTH_IN-1:0] in,
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input strobe_in,
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output reg [WIDTH_OUT-1:0] out = 0,
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output reg strobe_out = 0
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);
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localparam ERR_WIDTH = WIDTH_IN - WIDTH_OUT + 1;
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wire [ERR_WIDTH-1:0] err;
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wire [WIDTH_IN-1:0] err_ext, err_ext_01, sum;
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wire [WIDTH_OUT-1:0] out_pre;
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wire strobe_pre;
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sign_extend #(
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.bits_in (ERR_WIDTH),
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.bits_out (WIDTH_IN)
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) ext_err (
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.in (err),
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.out (err_ext)
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);
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assign err_ext_01 =
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//synthesis translate_off
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// Disallow X from getting stuck on the err_ext feedback path in simulation
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(^err_ext === 1'bX) ? 0 :
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//synthesis translate_on
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err_ext;
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add2_and_clip_reg #(
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.WIDTH (WIDTH_IN)
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) add2_and_clip_reg (
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.clk (clk),
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.rst (reset),
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.in1 (in),
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.in2 ((DISABLE_SD == 0) ? err_ext_01 : {WIDTH_IN{1'b0}}),
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.strobe_in (strobe_in),
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.sum (sum),
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.strobe_out (strobe_pre)
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);
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round #(
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.bits_in (WIDTH_IN),
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.bits_out (WIDTH_OUT)
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) round_sum (
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.in (sum),
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.out (out_pre),
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.err (err)
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);
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always @(posedge clk) begin
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if (reset) begin
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strobe_out <= 1'b0;
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end else begin
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strobe_out <= strobe_pre;
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if (strobe_pre) begin
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out <= out_pre;
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end
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end
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end
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endmodule // round_sd
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