adf6f576c6
FPGA: - Split up MB registers that control daughterboard specific settings so that daughterboards 0 and 1 could have different setings, in preparation for future devices that require different settings. This requires a compat number bump to 8.0. - Add registers for additional RFDC information, including the block/tile mapping of the individual channels, and information about resampling capabilities - Identify sections of code that would be specific to X410/ZBX and move them to their own headers, so it's trivial to add device-specific sections of code instead for other devices in the future. - This includes constraints for clocks and I/O pins. - Remove ability to do timed ctrlport transactions to the MB CPLD, this was unused and possibly broken. - Move daughterboard-specific code into its own code location (dboards/zbx) - Move X410-specific register documentation to its own location (doc/X410) - Refactor Makefiles to split out X410/ZBX specific components and allow switching between device types - Add 512-bit AXI interconnects - Make number of timekeepers configurable (X410 keeps the single timekeeper) MPM: - Required compat is bumped to 8.0 - Now supports new registers for detecting DSP capabilities and multi-rate settings for the daughterboards - Adds MMCM controls (currently unused) Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223
145 lines
6.3 KiB
Tcl
145 lines
6.3 KiB
Tcl
#
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# Copyright 2021 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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# Description:
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# Common pin constraints for X410.
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#
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###############################################################################
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# Pin constraints for the MGTs reference clocks
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###############################################################################
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set_property PACKAGE_PIN U33 [get_ports {MGT_REFCLK_LMK0_P}]
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set_property PACKAGE_PIN U34 [get_ports {MGT_REFCLK_LMK0_N}]
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set_property PACKAGE_PIN T31 [get_ports {MGT_REFCLK_LMK1_P}]
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set_property PACKAGE_PIN T32 [get_ports {MGT_REFCLK_LMK1_N}]
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set_property PACKAGE_PIN W33 [get_ports {MGT_REFCLK_LMK2_P}]
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set_property PACKAGE_PIN W34 [get_ports {MGT_REFCLK_LMK2_N}]
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set_property PACKAGE_PIN V31 [get_ports {MGT_REFCLK_LMK3_P}]
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set_property PACKAGE_PIN V32 [get_ports {MGT_REFCLK_LMK3_N}]
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###############################################################################
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# Common pin constraints for the QSFP28 ports
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###############################################################################
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set_property PACKAGE_PIN AJ15 [get_ports {QSFP0_MODPRS_n}]
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set_property PACKAGE_PIN AH16 [get_ports {QSFP0_RESET_n}]
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set_property PACKAGE_PIN AH15 [get_ports {QSFP0_LPMODE_n}]
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set_property PACKAGE_PIN AL11 [get_ports {QSFP1_MODPRS_n}]
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set_property PACKAGE_PIN AR8 [get_ports {QSFP1_RESET_n}]
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set_property PACKAGE_PIN AT9 [get_ports {QSFP1_LPMODE_n}]
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set_property IOSTANDARD LVCMOS12 [get_ports {QSFP*_MODPRS_n QSFP*_RESET_n QSFP*_LPMODE_n}]
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set_property SLEW SLOW [get_ports {QSFP*_RESET_n QSFP*_LPMODE_n}]
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###############################################################################
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# eCPRI future clocks
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###############################################################################
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# Input
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set_property PACKAGE_PIN AK17 [get_ports {FPGA_AUX_REF}]
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set_property IOSTANDARD LVCMOS12 [get_ports {FPGA_AUX_REF}]
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# Output
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set_property PACKAGE_PIN AG17 [get_ports {FABRIC_CLK_OUT_P}]
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set_property PACKAGE_PIN AH17 [get_ports {FABRIC_CLK_OUT_N}]
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set_property IOSTANDARD DIFF_SSTL12 [get_ports {FABRIC_CLK_OUT_*}]
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# GTY_RCV_CLK_P is defined in qsfp_port1
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###############################################################################
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# Pin constraints for the other PL pins (1.8 V)
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###############################################################################
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set_property PACKAGE_PIN A7 [get_ports {DB1_SYNTH_SYNC}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB1_SYNTH_SYNC}]
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set_property PACKAGE_PIN AP5 [get_ports {DB0_SYNTH_SYNC}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB0_SYNTH_SYNC}]
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set_property PACKAGE_PIN A9 [get_ports {LMK_SYNC}]
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set_property IOB TRUE [get_ports {LMK_SYNC}]
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set_property PACKAGE_PIN A10 [get_ports {TRIG_IO}]
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set_property PACKAGE_PIN A6 [get_ports {PPS_IN}]
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set_property PACKAGE_PIN AR7 [get_ports {PL_CPLD_SCLK}]
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set_property PACKAGE_PIN AR6 [get_ports {PL_CPLD_MOSI}]
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set_property PACKAGE_PIN AP6 [get_ports {PL_CPLD_MISO}]
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set_property IOSTANDARD LVCMOS18 [get_ports {LMK_SYNC TRIG_IO PPS_IN PL_CPLD_SCLK PL_CPLD_MOSI PL_CPLD_MISO}]
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set_property DRIVE 16 [get_ports {PL_CPLD_SCLK}]
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###############################################################################
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# Pin constraints for the other PL pins (1.2 V)
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###############################################################################
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set_property PACKAGE_PIN AL16 [get_ports {PLL_REFCLK_FPGA_P}]
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set_property PACKAGE_PIN AL15 [get_ports {PLL_REFCLK_FPGA_N}]
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set_property IOSTANDARD DIFF_SSTL12 [get_ports {PLL_REFCLK_FPGA_*}]
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set_property PACKAGE_PIN G17 [get_ports {BASE_REFCLK_FPGA_P}]
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set_property PACKAGE_PIN F17 [get_ports {BASE_REFCLK_FPGA_N}]
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set_property IOSTANDARD DIFF_SSTL12 [get_ports {BASE_REFCLK_FPGA_*}]
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set_property PACKAGE_PIN AF17 [get_ports {SYSREF_FABRIC_P}]
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set_property PACKAGE_PIN AF16 [get_ports {SYSREF_FABRIC_N}]
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set_property IOSTANDARD DIFF_SSTL12 [get_ports {SYSREF_FABRIC_*}]
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set_property PACKAGE_PIN J15 [get_ports {DIOA_FPGA[0]}]
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set_property PACKAGE_PIN H15 [get_ports {DIOA_FPGA[1]}]
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set_property PACKAGE_PIN L17 [get_ports {DIOA_FPGA[2]}]
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set_property PACKAGE_PIN K17 [get_ports {DIOA_FPGA[3]}]
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set_property PACKAGE_PIN K16 [get_ports {DIOA_FPGA[4]}]
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set_property PACKAGE_PIN J16 [get_ports {DIOA_FPGA[5]}]
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set_property PACKAGE_PIN K19 [get_ports {DIOA_FPGA[6]}]
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set_property PACKAGE_PIN K18 [get_ports {DIOA_FPGA[7]}]
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set_property PACKAGE_PIN H17 [get_ports {DIOA_FPGA[8]}]
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set_property PACKAGE_PIN H16 [get_ports {DIOA_FPGA[9]}]
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set_property PACKAGE_PIN J19 [get_ports {DIOA_FPGA[10]}]
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set_property PACKAGE_PIN J18 [get_ports {DIOA_FPGA[11]}]
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set_property PACKAGE_PIN M18 [get_ports {DIOB_FPGA[0]}]
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set_property PACKAGE_PIN H18 [get_ports {DIOB_FPGA[1]}]
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set_property PACKAGE_PIN G18 [get_ports {DIOB_FPGA[2]}]
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set_property PACKAGE_PIN G15 [get_ports {DIOB_FPGA[3]}]
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set_property PACKAGE_PIN F15 [get_ports {DIOB_FPGA[4]}]
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set_property PACKAGE_PIN G19 [get_ports {DIOB_FPGA[5]}]
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set_property PACKAGE_PIN F19 [get_ports {DIOB_FPGA[6]}]
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set_property PACKAGE_PIN F16 [get_ports {DIOB_FPGA[7]}]
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set_property PACKAGE_PIN E16 [get_ports {DIOB_FPGA[8]}]
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set_property PACKAGE_PIN E18 [get_ports {DIOB_FPGA[9]}]
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set_property PACKAGE_PIN E17 [get_ports {DIOB_FPGA[10]}]
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set_property PACKAGE_PIN E19 [get_ports {DIOB_FPGA[11]}]
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set_property IOSTANDARD LVCMOS12 [get_ports {DIO*_FPGA[*]}]
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set_property PULLDOWN true [get_ports {DIO*_FPGA[*]}]
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set_property PACKAGE_PIN AW13 [get_ports {PPS_LED}]
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set_property IOSTANDARD LVCMOS12 [get_ports {PPS_LED}]
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set_property PACKAGE_PIN B23 [get_ports {PL_CPLD_JTAGEN}]
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set_property PACKAGE_PIN N21 [get_ports {PL_CPLD_CS0_n}]
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set_property PACKAGE_PIN J24 [get_ports {PL_CPLD_CS1_n}]
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set_property PACKAGE_PIN AN12 [get_ports {CPLD_JTAG_OE_n}]
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set_property IOSTANDARD LVCMOS12 [get_ports {PL_CPLD_JTAGEN PL_CPLD_CS*_n CPLD_JTAG_OE_n}]
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###############################################################################
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# Unused pins
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###############################################################################
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# set_property PACKAGE_PIN D19 [get_ports {PL_CPLD_IRQ}]
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# set_property PACKAGE_PIN AF15 [get_ports {FPGA_TEST}]
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# set_property IOSTANDARD LVCMOS12 [get_ports {FPGA_TEST PL_CPLD_IRQ}]
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# set_property PACKAGE_PIN AK16 [get_ports {TDC_SPARE_0}]
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# set_property PACKAGE_PIN AJ16 [get_ports {TDC_SPARE_1}]
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# set_property IOSTANDARD LVCMOS12 [get_ports {TDC_SPARE_*}]
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