Wade Fife
81f150213f
This replaces the legacy RFNoC FFT block with a new one of the same name that includes a superset of the original features. New features include cyclic prefix insertion or removal and FFT sizes up to 64k. Original-commit: 25fffb006755b2e91f0138eb4af3ab9e16b8690c
77 lines
2.4 KiB
Makefile
77 lines
2.4 KiB
Makefile
#
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# Copyright 2024 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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#-------------------------------------------------
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# Top-of-Makefile
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#-------------------------------------------------
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# Define BASE_DIR to point to the "top" dir
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BASE_DIR = $(abspath ../../../../top)
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# Include viv_sim_preamble after defining BASE_DIR
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include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
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#-------------------------------------------------
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# IP Specific
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#-------------------------------------------------
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# If simulation contains IP, define the IP_DIR and point
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# it to the base level IP directory
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LIB_IP_DIR = $(BASE_DIR)/../lib/ip
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# Include makefiles and sources for all IP components
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# *after* defining the LIB_IP_DIR
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include $(LIB_IP_DIR)/xfft_64k_16b/Makefile.inc
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include $(LIB_IP_DIR)/xfft_32k_16b/Makefile.inc
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include $(LIB_IP_DIR)/xfft_16k_16b/Makefile.inc
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include $(LIB_IP_DIR)/xfft_8k_16b/Makefile.inc
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include $(LIB_IP_DIR)/xfft_4k_16b/Makefile.inc
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include $(LIB_IP_DIR)/xfft_2k_16b/Makefile.inc
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include $(LIB_IP_DIR)/xfft_1k_16b/Makefile.inc
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include $(LIB_IP_DIR)/complex_to_magphase_int17/Makefile.inc
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DESIGN_SRCS += $(abspath \
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$(LIB_IP_XFFT_64K_16B_OUTS) \
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$(LIB_IP_XFFT_32K_16B_OUTS) \
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$(LIB_IP_XFFT_16K_16B_OUTS) \
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$(LIB_IP_XFFT_8K_16B_OUTS) \
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$(LIB_IP_XFFT_4K_16B_OUTS) \
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$(LIB_IP_XFFT_3K_16B_OUTS) \
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$(LIB_IP_XFFT_2K_16B_OUTS) \
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$(LIB_IP_XFFT_1K_16B_OUTS) \
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$(LIB_IP_COMPLEX_TO_MAGPHASE_INT17_OUTS) \
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)
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#-------------------------------------------------
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# Design Specific
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#-------------------------------------------------
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# Include makefiles and sources for the DUT and its
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# dependencies.
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include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs
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include Makefile.srcs
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DESIGN_SRCS += $(abspath \
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$(RFNOC_CORE_SRCS) \
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$(RFNOC_UTIL_SRCS) \
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$(RFNOC_OOT_SRCS) \
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)
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#-------------------------------------------------
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# Testbench Specific
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#-------------------------------------------------
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SIM_TOP = rfnoc_block_fft_all_tb glbl
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SIM_SRCS = $(abspath \
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rfnoc_block_fft_tb.sv \
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rfnoc_block_fft_all_tb.sv \
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$(VIVADO_PATH)/data/verilog/src/glbl.v \
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)
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#-------------------------------------------------
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# Bottom-of-Makefile
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#-------------------------------------------------
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# Include all simulator specific makefiles here
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# Each should define a unique target to simulate
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# e.g. xsim, vsim, etc and a common "clean" target
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include $(BASE_DIR)/../tools/make/viv_simulator.mak
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