Martin Braun
cf85a6d40c
Cores originate from https://github.com/secworks/sha256. Original-commit: c43c72db097cbb5ebe29b7fa81484cbeaf19516b
243 lines
7.7 KiB
Verilog
243 lines
7.7 KiB
Verilog
//======================================================================
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//
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// sha256_w_mem_regs.v
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// -------------------
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// The W memory. This version uses 16 32-bit registers as a sliding
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// window to generate the 64 words.
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//
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//
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// Author: Joachim Strombergson
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// Copyright (c) 2013, Secworks Sweden AB
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or
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// without modification, are permitted provided that the following
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// conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//======================================================================
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`default_nettype none
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module sha256_w_mem(
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input wire clk,
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input wire reset_n,
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input wire [511 : 0] block,
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input wire [5 : 0] round,
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input wire init,
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input wire next,
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output wire [31 : 0] w
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);
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//----------------------------------------------------------------
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// Registers including update variables and write enable.
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//----------------------------------------------------------------
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reg [31 : 0] w_mem [0 : 15];
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reg [31 : 0] w_mem00_new;
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reg [31 : 0] w_mem01_new;
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reg [31 : 0] w_mem02_new;
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reg [31 : 0] w_mem03_new;
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reg [31 : 0] w_mem04_new;
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reg [31 : 0] w_mem05_new;
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reg [31 : 0] w_mem06_new;
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reg [31 : 0] w_mem07_new;
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reg [31 : 0] w_mem08_new;
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reg [31 : 0] w_mem09_new;
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reg [31 : 0] w_mem10_new;
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reg [31 : 0] w_mem11_new;
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reg [31 : 0] w_mem12_new;
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reg [31 : 0] w_mem13_new;
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reg [31 : 0] w_mem14_new;
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reg [31 : 0] w_mem15_new;
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reg w_mem_we;
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//----------------------------------------------------------------
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// Wires.
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//----------------------------------------------------------------
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reg [31 : 0] w_tmp;
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reg [31 : 0] w_new;
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//----------------------------------------------------------------
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// Concurrent connectivity for ports etc.
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//----------------------------------------------------------------
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assign w = w_tmp;
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//----------------------------------------------------------------
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// reg_update
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// Update functionality for all registers in the core.
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// All registers are positive edge triggered with synchronous
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// active low reset. All registers have write enable.
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//----------------------------------------------------------------
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always @ (posedge clk or negedge reset_n)
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begin : reg_update
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integer i;
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if (!reset_n)
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begin
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for (i = 0 ; i < 16 ; i = i + 1) begin
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w_mem[i] <= 32'h0;
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end
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end
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else
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begin
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if (w_mem_we)
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begin
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w_mem[00] <= w_mem00_new;
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w_mem[01] <= w_mem01_new;
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w_mem[02] <= w_mem02_new;
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w_mem[03] <= w_mem03_new;
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w_mem[04] <= w_mem04_new;
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w_mem[05] <= w_mem05_new;
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w_mem[06] <= w_mem06_new;
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w_mem[07] <= w_mem07_new;
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w_mem[08] <= w_mem08_new;
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w_mem[09] <= w_mem09_new;
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w_mem[10] <= w_mem10_new;
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w_mem[11] <= w_mem11_new;
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w_mem[12] <= w_mem12_new;
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w_mem[13] <= w_mem13_new;
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w_mem[14] <= w_mem14_new;
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w_mem[15] <= w_mem15_new;
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end
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end
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end // reg_update
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//----------------------------------------------------------------
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// select_w
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//
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// Mux for the external read operation. This is where we exract
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// the W variable.
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//----------------------------------------------------------------
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always @*
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begin : select_w
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if (round < 16)
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w_tmp = w_mem[round[3 : 0]];
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else
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w_tmp = w_new;
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end // select_w
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//----------------------------------------------------------------
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// w_new_logic
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//
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// Logic that calculates the next value to be inserted into
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// the sliding window of the memory.
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//----------------------------------------------------------------
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always @*
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begin : w_mem_update_logic
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reg [31 : 0] w_0;
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reg [31 : 0] w_1;
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reg [31 : 0] w_9;
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reg [31 : 0] w_14;
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reg [31 : 0] d0;
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reg [31 : 0] d1;
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w_mem00_new = 32'h0;
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w_mem01_new = 32'h0;
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w_mem02_new = 32'h0;
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w_mem03_new = 32'h0;
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w_mem04_new = 32'h0;
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w_mem05_new = 32'h0;
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w_mem06_new = 32'h0;
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w_mem07_new = 32'h0;
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w_mem08_new = 32'h0;
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w_mem09_new = 32'h0;
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w_mem10_new = 32'h0;
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w_mem11_new = 32'h0;
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w_mem12_new = 32'h0;
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w_mem13_new = 32'h0;
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w_mem14_new = 32'h0;
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w_mem15_new = 32'h0;
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w_mem_we = 0;
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w_0 = w_mem[0];
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w_1 = w_mem[1];
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w_9 = w_mem[9];
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w_14 = w_mem[14];
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d0 = {w_1[6 : 0], w_1[31 : 7]} ^
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{w_1[17 : 0], w_1[31 : 18]} ^
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{3'b000, w_1[31 : 3]};
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d1 = {w_14[16 : 0], w_14[31 : 17]} ^
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{w_14[18 : 0], w_14[31 : 19]} ^
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{10'b0000000000, w_14[31 : 10]};
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w_new = d1 + w_9 + d0 + w_0;
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if (init)
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begin
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w_mem00_new = block[511 : 480];
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w_mem01_new = block[479 : 448];
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w_mem02_new = block[447 : 416];
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w_mem03_new = block[415 : 384];
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w_mem04_new = block[383 : 352];
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w_mem05_new = block[351 : 320];
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w_mem06_new = block[319 : 288];
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w_mem07_new = block[287 : 256];
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w_mem08_new = block[255 : 224];
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w_mem09_new = block[223 : 192];
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w_mem10_new = block[191 : 160];
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w_mem11_new = block[159 : 128];
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w_mem12_new = block[127 : 96];
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w_mem13_new = block[95 : 64];
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w_mem14_new = block[63 : 32];
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w_mem15_new = block[31 : 0];
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w_mem_we = 1;
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end
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if (next && (round > 15))
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begin
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w_mem00_new = w_mem[01];
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w_mem01_new = w_mem[02];
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w_mem02_new = w_mem[03];
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w_mem03_new = w_mem[04];
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w_mem04_new = w_mem[05];
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w_mem05_new = w_mem[06];
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w_mem06_new = w_mem[07];
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w_mem07_new = w_mem[08];
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w_mem08_new = w_mem[09];
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w_mem09_new = w_mem[10];
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w_mem10_new = w_mem[11];
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w_mem11_new = w_mem[12];
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w_mem12_new = w_mem[13];
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w_mem13_new = w_mem[14];
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w_mem14_new = w_mem[15];
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w_mem15_new = w_new;
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w_mem_we = 1;
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end
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end // w_mem_update_logic
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endmodule // sha256_w_mem
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`default_nettype wire
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//======================================================================
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// sha256_w_mem.v
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//======================================================================
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