Martin Braun
ec4fab0340
- 2to3 was used to convert the Python scripts, except where the tool choked and manual intervention was required - All references to "python" where replaced with "python3" - buffer() was replaced by memoryview() Original-commit: ca68195b5d12c5410cfac8d459a0b0902c4c72c7
262 lines
11 KiB
Python
Executable File
262 lines
11 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# Copyright 2016 Ettus Research
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#
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# This program is free software: you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation, either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <http://www.gnu.org/licenses/>.
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#
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import math
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import rfnocsim
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class UsrpX310(rfnocsim.SimComp):
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# Hardware specific constants
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RADIO_LATENCY = 1e-6
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IO_LATENCY = 1e-6
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MAX_SAMP_RATE = 300e6 # Limited by 10GbE
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BPI = 4 # Bytes per sample (item)
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"""
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Simulation model for the USRP X310
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- Has two producers and consumers of FFT data
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- Computes bandwidth and latency using FFT size and overlap
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"""
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def __init__(self, sim_core, index, app_settings):
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rfnocsim.SimComp.__init__(self, sim_core, name='USRP_%03d' % (index), ctype=rfnocsim.comptype.hardware)
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# USRP i carries data for radio 2i and 2i+1 interleaved into one stream
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self.index = index
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items = [rfnocsim.DataStream.submatrix_gen('rx', [2*index]),
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rfnocsim.DataStream.submatrix_gen('rx', [2*index+1])]
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# Samples are 4 bytes I and Q
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latency = (self.RADIO_LATENCY + self.IO_LATENCY/2) * self.get_tick_rate()
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if app_settings['domain'] == 'frequency':
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# Max latency per direction depends on the FFT size and sample rate
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latency += self.__get_fft_latency(
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app_settings['fft_size'], app_settings['samp_rate'], self.get_tick_rate())
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# An X310 Radio has two producers (RX data) and consumers (TX data) (i.e. two ethernet ports)
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# Both ports can carry data from both radio frontends
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self.sources = ([
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rfnocsim.Producer(sim_core, self.name + '/TX0', self.BPI, items, self.MAX_SAMP_RATE, latency),
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rfnocsim.Producer(sim_core, self.name + '/TX1', self.BPI, items, self.MAX_SAMP_RATE, latency)])
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self.sinks = ([
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rfnocsim.Consumer(sim_core, self.name + '/RX0', self.BPI * self.MAX_SAMP_RATE, latency),
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rfnocsim.Consumer(sim_core, self.name + '/RX1', self.BPI * self.MAX_SAMP_RATE, latency)])
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# The actual sample rate depends over the wire depends on the radio sample rate,
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# the FFT size and FFT overlap
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for src in self.sources:
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if app_settings['domain'] == 'frequency':
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src.set_rate(app_settings['samp_rate'] *
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(1.0 + (float(app_settings['fft_overlap'])/app_settings['fft_size'])))
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else:
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src.set_rate(app_settings['samp_rate'])
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def inputs(self, i, bind=False):
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return self.sinks[i].inputs(0, bind)
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def connect(self, i, dest):
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self.sources[i].connect(0, dest)
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def get_utilization(self, what):
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return 0.0
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def get_util_attrs(self):
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return []
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def validate(self, chan):
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recvd = self.sinks[chan].get_items()
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idxs = []
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for i in recvd:
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(str_id, idx) = rfnocsim.DataStream.submatrix_parse(i)
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if str_id != 'tx':
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raise RuntimeError(self.name + ' received incorrect TX data on channel ' + str(chan))
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idxs.append(idx[0][0])
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if sorted(idxs) != [self.index*2, self.index*2 + 1]:
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raise RuntimeError(self.name + ' received incorrect TX data. Got: ' + str(sorted(idxs)))
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def __get_fft_latency(self, fft_size, samp_rate, tick_rate):
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FFT_CLK_RATE = 200e6
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fft_cycles = {128:349, 256:611, 512:1133, 1024:2163, 2048:4221, 4096:8323}
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latency = max(
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fft_cycles[fft_size] / FFT_CLK_RATE, #Min time to leave FFT
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fft_size / samp_rate) #Min time to enter FFT
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return latency * tick_rate
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class Bee7Fpga(rfnocsim.SimComp):
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"""
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Simulation model for a single Beecube BEE7 FPGA
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- Type = hardware
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- Contains 80 IO lanes per FPGA: 16 each to neighboring
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FPGAs and 32 lanes going outside
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"""
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# IO lanes (How the various IO lanes in an FPGA are allocated)
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EW_IO_LANES = list(range(0,16))
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NS_IO_LANES = list(range(16,32))
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XX_IO_LANES = list(range(32,48))
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EXT_IO_LANES = list(range(48,80))
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# External IO lane connections
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FP_BASE = 0 # Front panel FMC
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FP_LANES = 16
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BP_BASE = 16 # Backplane RTM
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BP_LANES = 16
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# Hardware specific constants
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IO_LN_LATENCY = 1.5e-6
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IO_LN_BW = 10e9/8
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ELASTIC_BUFF_FULLNESS = 0.5
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BRAM_BYTES = 18e3/8
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def __init__(self, sim_core, name):
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self.sim_core = sim_core
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rfnocsim.SimComp.__init__(self, sim_core, name, rfnocsim.comptype.hardware)
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# Max resources from Virtex7 datasheet
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self.max_resources = rfnocsim.HwRsrcs()
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self.max_resources.add('DSP', 3600)
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self.max_resources.add('BRAM_18kb', 2940)
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self.resources = rfnocsim.HwRsrcs()
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# Each FPGA has 80 SERDES lanes
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self.max_io = 80
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self.serdes_i = dict()
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self.serdes_o = dict()
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# Each lane can carry at most 10GB/s
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# Each SERDES needs to have some buffering. We assume elastic buffering (50% full on avg).
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io_buff_size = (self.IO_LN_BW * self.IO_LN_LATENCY) / self.ELASTIC_BUFF_FULLNESS
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# Worst case lane latency
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lane_latency = self.IO_LN_LATENCY * self.get_tick_rate()
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for i in range(self.max_io):
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self.serdes_i[i] = rfnocsim.Channel(sim_core, self.__ioln_name(i)+'/I', self.IO_LN_BW, lane_latency / 2)
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self.serdes_o[i] = rfnocsim.Channel(sim_core, self.__ioln_name(i)+'/O', self.IO_LN_BW, lane_latency / 2)
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self.resources.add('BRAM_18kb', 1 + math.ceil(io_buff_size / self.BRAM_BYTES)) #input buffering per lane
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self.resources.add('BRAM_18kb', 1) #output buffering per lane
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# Other resources
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self.resources.add('BRAM_18kb', 72) # BPS infrastructure + microblaze
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self.resources.add('BRAM_18kb', 128) # 2 MIGs
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self.functions = dict()
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def inputs(self, i, bind=False):
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return self.serdes_i[i].inputs(0, bind)
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def connect(self, i, dest):
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self.serdes_o[i].connect(0, dest)
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def get_utilization(self, what):
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if self.max_resources.get(what) != 0:
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return self.resources.get(what) / self.max_resources.get(what)
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else:
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return 0.0
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def get_util_attrs(self):
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return ['DSP', 'BRAM_18kb']
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def rename(self, name):
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self.name = name
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def add_function(self, func):
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if func.name not in self.functions:
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self.functions[func.name] = func
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else:
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raise RuntimeError('Function ' + self.name + ' already defined in ' + self.name)
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self.resources.merge(func.get_rsrcs())
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def __ioln_name(self, i):
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if i in self.EW_IO_LANES:
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return '%s/SER_EW_%02d'%(self.name,i-self.EW_IO_LANES[0])
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elif i in self.NS_IO_LANES:
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return '%s/SER_NS_%02d'%(self.name,i-self.NS_IO_LANES[0])
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elif i in self.XX_IO_LANES:
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return '%s/SER_XX_%02d'%(self.name,i-self.XX_IO_LANES[0])
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else:
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return '%s/SER_EXT_%02d'%(self.name,i-self.EXT_IO_LANES[0])
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class Bee7Blade(rfnocsim.SimComp):
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"""
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Simulation model for a single Beecube BEE7
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- Contains 4 FPGAs (fully connected with 16 lanes)
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"""
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NUM_FPGAS = 4
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# FPGA positions in the blade
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NW_FPGA = 0
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NE_FPGA = 1
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SW_FPGA = 2
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SE_FPGA = 3
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def __init__(self, sim_core, index):
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self.sim_core = sim_core
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self.name = name='BEE7_%03d' % (index)
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# Add FPGAs
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names = ['FPGA_NW', 'FPGA_NE', 'FPGA_SW', 'FPGA_SE']
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self.fpgas = []
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for i in range(self.NUM_FPGAS):
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self.fpgas.append(Bee7Fpga(sim_core, name + '/' + names[i]))
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# Build a fully connected network of FPGA
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# 4 FPGAs x 3 Links x 2 directions = 12 connections
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self.sim_core.connect_multi_bidir(
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self.fpgas[self.NW_FPGA], Bee7Fpga.EW_IO_LANES, self.fpgas[self.NE_FPGA], Bee7Fpga.EW_IO_LANES)
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self.sim_core.connect_multi_bidir(
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self.fpgas[self.NW_FPGA], Bee7Fpga.NS_IO_LANES, self.fpgas[self.SW_FPGA], Bee7Fpga.NS_IO_LANES)
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self.sim_core.connect_multi_bidir(
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self.fpgas[self.NW_FPGA], Bee7Fpga.XX_IO_LANES, self.fpgas[self.SE_FPGA], Bee7Fpga.XX_IO_LANES)
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self.sim_core.connect_multi_bidir(
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self.fpgas[self.NE_FPGA], Bee7Fpga.XX_IO_LANES, self.fpgas[self.SW_FPGA], Bee7Fpga.XX_IO_LANES)
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self.sim_core.connect_multi_bidir(
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self.fpgas[self.NE_FPGA], Bee7Fpga.NS_IO_LANES, self.fpgas[self.SE_FPGA], Bee7Fpga.NS_IO_LANES)
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self.sim_core.connect_multi_bidir(
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self.fpgas[self.SW_FPGA], Bee7Fpga.EW_IO_LANES, self.fpgas[self.SE_FPGA], Bee7Fpga.EW_IO_LANES)
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def inputs(self, i, bind=False):
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IO_PER_FPGA = len(Bee7Fpga.EXT_IO_LANES)
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return self.fpgas[int(i/IO_PER_FPGA)].inputs(Bee7Fpga.EXT_IO_LANES[i%IO_PER_FPGA], bind)
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def connect(self, i, dest):
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IO_PER_FPGA = len(Bee7Fpga.EXT_IO_LANES)
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self.fpgas[int(i/IO_PER_FPGA)].connect(Bee7Fpga.EXT_IO_LANES[i%IO_PER_FPGA], dest)
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@staticmethod
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def io_lane(fpga, fpga_lane):
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IO_PER_FPGA = len(Bee7Fpga.EXT_IO_LANES)
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return (fpga_lane - Bee7Fpga.EXT_IO_LANES[0]) + (fpga * IO_PER_FPGA)
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class ManagementHostandSwitch(rfnocsim.SimComp):
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"""
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Simulation model for a management host computer
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- Sources channel coefficients
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- Configures radio
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"""
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def __init__(self, sim_core, index, num_coeffs, switch_ports, app_settings):
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rfnocsim.SimComp.__init__(self, sim_core, name='MGMT_HOST_%03d'%(index), ctype=rfnocsim.comptype.other)
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if app_settings['domain'] == 'frequency':
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k = app_settings['fft_size']
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else:
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k = app_settings['fir_taps']
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self.sources = dict()
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self.sinks = dict()
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for l in range(switch_ports):
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self.sources[l] = rfnocsim.Producer(
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sim_core, '%s/COEFF_%d'%(self.name,l), 4, ['coeff_%03d[%d]'%(index,l)], (10e9/8)/switch_ports, 0)
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self.sinks[l] = rfnocsim.Consumer(sim_core, self.name + '%s/ACK%d'%(self.name,l))
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self.sources[l].set_rate(k*num_coeffs*app_settings['coherence_rate'])
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def inputs(self, i, bind=False):
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return self.sinks[i].inputs(0, bind)
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def connect(self, i, dest):
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self.sources[i].connect(0, dest)
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def get_utilization(self, what):
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return 0.0
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def get_util_attrs(self):
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return []
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