+18









Martin Braun
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
6b67702ad7
The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Andrej Rode <andrej.rode@ettus.com> Co-authored-by: Ashish Chaudhari <ashish@ettus.com> Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ettus.com> Co-authored-by: EJ Kreinar <ej@he360.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Ian Buckley <ian.buckley@gmail.com> Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Jon Kiser <jon.kiser@ni.com> Co-authored-by: Josh Blum <josh@joshknows.com> Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Matt Ettus <matt@ettus.com> Co-authored-by: Michael West <michael.west@ettus.com> Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com> Co-authored-by: Nick Foster <nick@ettus.com> Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Paul David <paul.david@ettus.com> Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com> Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com> Co-authored-by: Sylvain Munaut <tnt@246tNt.com> Co-authored-by: Trung Tran <trung.tran@ettus.com> Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
87 lines
2.5 KiB
Verilog
87 lines
2.5 KiB
Verilog
//
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// Copyright 2018 Ettus Research, A National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: chdr_compute_tkeep
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// Description:
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// This module monitors an AXI-Stream CHDR bus and uses the
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// packet size field in the CHDR header to compute a tkeep
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// trailer signal to indicate the the valid bytes when
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// tlast is asserted.
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//
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// Parameters:
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// - CHDR_W: Width of the CHDR bus in bits
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// - ITEM_W: Width of the item bus in bits (must be a multiple of 8)
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//
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// Signals:
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// - axis_* : AXI-Stream CHDR bus
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module chdr_compute_tkeep #(
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parameter CHDR_W = 256,
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parameter ITEM_W = 32
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)(
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input wire clk,
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input wire rst,
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input wire [CHDR_W-1:0] axis_tdata,
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input wire axis_tlast,
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input wire axis_tvalid,
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input wire axis_tready,
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output wire [(CHDR_W/ITEM_W)-1:0] axis_tkeep
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);
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`include "rfnoc_chdr_utils.vh"
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generate if (CHDR_W > ITEM_W) begin
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localparam CHDR_W_BYTES = CHDR_W/8;
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localparam ITEM_W_BYTES = ITEM_W/8;
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localparam KEEP_W = CHDR_W_BYTES/ITEM_W_BYTES;
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// Binary to thermometer decoder
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// 2'd0 => 4'b1111 (special case)
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// 2'd1 => 4'b0001
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// 2'd2 => 4'b0011
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// 2'd3 => 4'b0111
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function [KEEP_W-1:0] bin2thermo;
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input [$clog2(KEEP_W)-1:0] bin;
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bin2thermo = ~((~1)<<((bin-1)%KEEP_W));
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endfunction
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// Read the packet length and figure out the number
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// of trailing items
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wire [15:0] pkt_len = chdr_get_length(axis_tdata[63:0]);
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wire [KEEP_W-1:0] len_thermo = bin2thermo(pkt_len[$clog2(CHDR_W_BYTES)-1:$clog2(ITEM_W_BYTES)]);
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reg [KEEP_W-1:0] reg_len_thermo = 'h0;
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reg is_header = 1'b1;
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always @(posedge clk) begin
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if (rst) begin
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is_header <= 1'b1;
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end else if (axis_tvalid & axis_tready) begin
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is_header <= axis_tlast;
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if (is_header) begin
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reg_len_thermo <= len_thermo;
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end
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end
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end
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// tkeep indicates trailing items, so for lines with tlast == 0,
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// tkeep is all 1's.
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assign axis_tkeep = (~axis_tlast) ? {KEEP_W{1'b1}} :
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(is_header ? len_thermo : reg_len_thermo);
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end else if (CHDR_W == ITEM_W) begin
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// Only one item per CHDR word. So always keep it.
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assign axis_tkeep = 1'b1;
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end else begin
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// Illegal. A item must be smaller than the CHDR_W
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illegal_parameter_value item_w_cannot_be_larger_than_chdr_w();
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end endgenerate
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endmodule // chdr_compute_tkeep
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