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Martin BraunAlex WilliamsAndrej RodeAshish ChaudhariBen HilburnCiro NishiguchiDaniel JepsonDerek KozelEJ KreinarHumberto JimenezIan BuckleyJörg HofrichterJon KiserJosh BlumJonathon PendlumMatt EttusMichael WestMoritz FischerNick FosterNicolas CuervoPaul ButlerPaul DavidRyan MarlowSugandha GuptaSylvain MunautTrung TranVidush VishwanathWade Fife
6b67702ad7
Martin BraunAlex WilliamsAndrej RodeAshish ChaudhariBen HilburnCiro NishiguchiDaniel JepsonDerek KozelEJ KreinarHumberto JimenezIan BuckleyJörg HofrichterJon KiserJosh BlumJonathon PendlumMatt EttusMichael WestMoritz FischerNick FosterNicolas CuervoPaul ButlerPaul DavidRyan MarlowSugandha GuptaSylvain MunautTrung TranVidush VishwanathWade FifeThe FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Andrej Rode <andrej.rode@ettus.com> Co-authored-by: Ashish Chaudhari <ashish@ettus.com> Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ettus.com> Co-authored-by: EJ Kreinar <ej@he360.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Ian Buckley <ian.buckley@gmail.com> Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Jon Kiser <jon.kiser@ni.com> Co-authored-by: Josh Blum <josh@joshknows.com> Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Matt Ettus <matt@ettus.com> Co-authored-by: Michael West <michael.west@ettus.com> Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com> Co-authored-by: Nick Foster <nick@ettus.com> Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Paul David <paul.david@ettus.com> Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com> Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com> Co-authored-by: Sylvain Munaut <tnt@246tNt.com> Co-authored-by: Trung Tran <trung.tran@ettus.com> Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
1063 lines
44 KiB
Verilog
1063 lines
44 KiB
Verilog
//
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// Copyright 2019 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: rfnoc_image_core (for n310)
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// This file was autogenerated by UHD's image builder tool (rfnoc_image_builder)
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// Re-running that tool will overwrite this file!
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// File generated on: 2019-11-08T15:58:13.073656
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// Source: ./n3xx/n310_rfnoc_image_core.yml
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// Source SHA256: a4a2464a5fdebb8ac35e78c2ea53ad7be23f8106376098188c9a4caeba8bcf0e
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module rfnoc_image_core #(
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parameter [15:0] PROTOVER = {8'd1, 8'd0}
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)(
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// Clocks
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input wire chdr_aclk,
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input wire ctrl_aclk,
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input wire core_arst,
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input wire radio_clk,
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input wire dram_clk,
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// Basic
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input wire [15:0] device_id,
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//// IO ports //////////////////////////////////
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// ctrlport_radio0
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output wire [ 1-1:0] m_ctrlport_radio0_req_wr,
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output wire [ 1-1:0] m_ctrlport_radio0_req_rd,
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output wire [ 20-1:0] m_ctrlport_radio0_req_addr,
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output wire [ 32-1:0] m_ctrlport_radio0_req_data,
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output wire [ 4-1:0] m_ctrlport_radio0_req_byte_en,
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output wire [ 1-1:0] m_ctrlport_radio0_req_has_time,
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output wire [ 64-1:0] m_ctrlport_radio0_req_time,
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input wire [ 1-1:0] m_ctrlport_radio0_resp_ack,
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input wire [ 2-1:0] m_ctrlport_radio0_resp_status,
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input wire [ 32-1:0] m_ctrlport_radio0_resp_data,
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// ctrlport_radio1
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output wire [ 1-1:0] m_ctrlport_radio1_req_wr,
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output wire [ 1-1:0] m_ctrlport_radio1_req_rd,
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output wire [ 20-1:0] m_ctrlport_radio1_req_addr,
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output wire [ 32-1:0] m_ctrlport_radio1_req_data,
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output wire [ 4-1:0] m_ctrlport_radio1_req_byte_en,
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output wire [ 1-1:0] m_ctrlport_radio1_req_has_time,
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output wire [ 64-1:0] m_ctrlport_radio1_req_time,
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input wire [ 1-1:0] m_ctrlport_radio1_resp_ack,
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input wire [ 2-1:0] m_ctrlport_radio1_resp_status,
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input wire [ 32-1:0] m_ctrlport_radio1_resp_data,
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// time_keeper
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input wire [ 64-1:0] radio_time,
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// x300_radio0
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input wire [ 64-1:0] radio_rx_data_radio0,
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input wire [ 2-1:0] radio_rx_stb_radio0,
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output wire [ 2-1:0] radio_rx_running_radio0,
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output wire [ 64-1:0] radio_tx_data_radio0,
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input wire [ 2-1:0] radio_tx_stb_radio0,
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output wire [ 2-1:0] radio_tx_running_radio0,
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// x300_radio1
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input wire [ 64-1:0] radio_rx_data_radio1,
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input wire [ 2-1:0] radio_rx_stb_radio1,
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output wire [ 2-1:0] radio_rx_running_radio1,
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output wire [ 64-1:0] radio_tx_data_radio1,
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input wire [ 2-1:0] radio_tx_stb_radio1,
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output wire [ 2-1:0] radio_tx_running_radio1,
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// dram
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input wire [ 1-1:0] axi_rst,
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output wire [ 4-1:0] m_axi_awid,
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output wire [128-1:0] m_axi_awaddr,
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output wire [ 32-1:0] m_axi_awlen,
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output wire [ 12-1:0] m_axi_awsize,
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output wire [ 8-1:0] m_axi_awburst,
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output wire [ 4-1:0] m_axi_awlock,
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output wire [ 16-1:0] m_axi_awcache,
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output wire [ 12-1:0] m_axi_awprot,
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output wire [ 16-1:0] m_axi_awqos,
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output wire [ 16-1:0] m_axi_awregion,
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output wire [ 4-1:0] m_axi_awuser,
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output wire [ 4-1:0] m_axi_awvalid,
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input wire [ 4-1:0] m_axi_awready,
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output wire [256-1:0] m_axi_wdata,
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output wire [ 32-1:0] m_axi_wstrb,
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output wire [ 4-1:0] m_axi_wlast,
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output wire [ 4-1:0] m_axi_wuser,
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output wire [ 4-1:0] m_axi_wvalid,
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input wire [ 4-1:0] m_axi_wready,
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input wire [ 4-1:0] m_axi_bid,
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input wire [ 8-1:0] m_axi_bresp,
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input wire [ 4-1:0] m_axi_buser,
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input wire [ 4-1:0] m_axi_bvalid,
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output wire [ 4-1:0] m_axi_bready,
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output wire [ 4-1:0] m_axi_arid,
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output wire [128-1:0] m_axi_araddr,
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output wire [ 32-1:0] m_axi_arlen,
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output wire [ 12-1:0] m_axi_arsize,
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output wire [ 8-1:0] m_axi_arburst,
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output wire [ 4-1:0] m_axi_arlock,
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output wire [ 16-1:0] m_axi_arcache,
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output wire [ 12-1:0] m_axi_arprot,
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output wire [ 16-1:0] m_axi_arqos,
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output wire [ 16-1:0] m_axi_arregion,
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output wire [ 4-1:0] m_axi_aruser,
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output wire [ 4-1:0] m_axi_arvalid,
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input wire [ 4-1:0] m_axi_arready,
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input wire [ 4-1:0] m_axi_rid,
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input wire [256-1:0] m_axi_rdata,
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input wire [ 8-1:0] m_axi_rresp,
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input wire [ 4-1:0] m_axi_rlast,
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input wire [ 4-1:0] m_axi_ruser,
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input wire [ 4-1:0] m_axi_rvalid,
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output wire [ 4-1:0] m_axi_rready,
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// Transport 0 (eth0 1G)
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input wire [64-1:0] s_eth0_tdata,
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input wire s_eth0_tlast,
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input wire s_eth0_tvalid,
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output wire s_eth0_tready,
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output wire [64-1:0] m_eth0_tdata,
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output wire m_eth0_tlast,
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output wire m_eth0_tvalid,
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input wire m_eth0_tready,
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// Transport 1 (eth1 10G)
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input wire [64-1:0] s_eth1_tdata,
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input wire s_eth1_tlast,
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input wire s_eth1_tvalid,
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output wire s_eth1_tready,
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output wire [64-1:0] m_eth1_tdata,
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output wire m_eth1_tlast,
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output wire m_eth1_tvalid,
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input wire m_eth1_tready,
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// Transport 2 (dma dma)
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input wire [64-1:0] s_dma_tdata,
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input wire s_dma_tlast,
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input wire s_dma_tvalid,
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output wire s_dma_tready,
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output wire [64-1:0] m_dma_tdata,
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output wire m_dma_tlast,
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output wire m_dma_tvalid,
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input wire m_dma_tready
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);
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localparam CHDR_W = 64;
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localparam MTU = 10;
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localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
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wire rfnoc_chdr_clk, rfnoc_chdr_rst;
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wire rfnoc_ctrl_clk, rfnoc_ctrl_rst;
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// ----------------------------------------------------
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// CHDR Crossbar
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// ----------------------------------------------------
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wire [CHDR_W-1:0] xb_to_ep0_tdata ;
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wire xb_to_ep0_tlast ;
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wire xb_to_ep0_tvalid;
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wire xb_to_ep0_tready;
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wire [CHDR_W-1:0] ep0_to_xb_tdata ;
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wire ep0_to_xb_tlast ;
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wire ep0_to_xb_tvalid;
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wire ep0_to_xb_tready;
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wire [CHDR_W-1:0] xb_to_ep1_tdata ;
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wire xb_to_ep1_tlast ;
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wire xb_to_ep1_tvalid;
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wire xb_to_ep1_tready;
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wire [CHDR_W-1:0] ep1_to_xb_tdata ;
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wire ep1_to_xb_tlast ;
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wire ep1_to_xb_tvalid;
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wire ep1_to_xb_tready;
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wire [CHDR_W-1:0] xb_to_ep2_tdata ;
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wire xb_to_ep2_tlast ;
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wire xb_to_ep2_tvalid;
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wire xb_to_ep2_tready;
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wire [CHDR_W-1:0] ep2_to_xb_tdata ;
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wire ep2_to_xb_tlast ;
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wire ep2_to_xb_tvalid;
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wire ep2_to_xb_tready;
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wire [CHDR_W-1:0] xb_to_ep3_tdata ;
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wire xb_to_ep3_tlast ;
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wire xb_to_ep3_tvalid;
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wire xb_to_ep3_tready;
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wire [CHDR_W-1:0] ep3_to_xb_tdata ;
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wire ep3_to_xb_tlast ;
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wire ep3_to_xb_tvalid;
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wire ep3_to_xb_tready;
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chdr_crossbar_nxn #(
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.CHDR_W (CHDR_W),
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.NPORTS (7),
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.DEFAULT_PORT (0),
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.MTU (MTU),
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.ROUTE_TBL_SIZE (6),
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.MUX_ALLOC ("ROUND-ROBIN"),
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.OPTIMIZE ("AREA"),
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.NPORTS_MGMT (3),
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.EXT_RTCFG_PORT (0),
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.PROTOVER (PROTOVER)
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) chdr_xb_i (
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.clk (rfnoc_chdr_clk),
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.reset (rfnoc_chdr_rst),
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.device_id (device_id),
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.s_axis_tdata ({ep3_to_xb_tdata, ep2_to_xb_tdata, ep1_to_xb_tdata, ep0_to_xb_tdata, s_dma_tdata, s_eth1_tdata, s_eth0_tdata}),
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.s_axis_tlast ({ep3_to_xb_tlast, ep2_to_xb_tlast, ep1_to_xb_tlast, ep0_to_xb_tlast, s_dma_tlast, s_eth1_tlast, s_eth0_tlast}),
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.s_axis_tvalid ({ep3_to_xb_tvalid, ep2_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, s_eth1_tvalid, s_eth0_tvalid}),
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.s_axis_tready ({ep3_to_xb_tready, ep2_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, s_eth1_tready, s_eth0_tready}),
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.m_axis_tdata ({xb_to_ep3_tdata, xb_to_ep2_tdata, xb_to_ep1_tdata, xb_to_ep0_tdata, m_dma_tdata, m_eth1_tdata, m_eth0_tdata}),
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.m_axis_tlast ({xb_to_ep3_tlast, xb_to_ep2_tlast, xb_to_ep1_tlast, xb_to_ep0_tlast, m_dma_tlast, m_eth1_tlast, m_eth0_tlast}),
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.m_axis_tvalid ({xb_to_ep3_tvalid, xb_to_ep2_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, m_eth1_tvalid, m_eth0_tvalid}),
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.m_axis_tready ({xb_to_ep3_tready, xb_to_ep2_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, m_eth1_tready, m_eth0_tready}),
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.ext_rtcfg_stb (1'h0),
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.ext_rtcfg_addr (16'h0),
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.ext_rtcfg_data (32'h0),
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.ext_rtcfg_ack ()
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);
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// ----------------------------------------------------
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// Stream Endpoints
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// ----------------------------------------------------
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wire [CHDR_W-1:0] m_ep0_out0_tdata;
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wire m_ep0_out0_tlast;
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wire m_ep0_out0_tvalid;
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wire m_ep0_out0_tready;
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wire [CHDR_W-1:0] s_ep0_in0_tdata;
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wire s_ep0_in0_tlast;
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wire s_ep0_in0_tvalid;
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wire s_ep0_in0_tready;
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wire [31:0] m_ep0_ctrl_tdata , s_ep0_ctrl_tdata ;
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wire m_ep0_ctrl_tlast , s_ep0_ctrl_tlast ;
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wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid;
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wire m_ep0_ctrl_tready, s_ep0_ctrl_tready;
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chdr_stream_endpoint #(
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.PROTOVER (PROTOVER),
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.CHDR_W (CHDR_W),
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.AXIS_CTRL_EN (1),
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.AXIS_DATA_EN (1),
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.NUM_DATA_I (1),
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.NUM_DATA_O (1),
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.INST_NUM (0),
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.CTRL_XBAR_PORT (1),
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.INGRESS_BUFF_SIZE (15),
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.MTU (MTU),
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.REPORT_STRM_ERRS (1)
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) ep0_i (
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.rfnoc_chdr_clk (rfnoc_chdr_clk ),
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.rfnoc_chdr_rst (rfnoc_chdr_rst ),
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.rfnoc_ctrl_clk (rfnoc_ctrl_clk ),
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.rfnoc_ctrl_rst (rfnoc_ctrl_rst ),
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.device_id (device_id ),
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.s_axis_chdr_tdata (xb_to_ep0_tdata ),
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.s_axis_chdr_tlast (xb_to_ep0_tlast ),
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.s_axis_chdr_tvalid (xb_to_ep0_tvalid ),
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.s_axis_chdr_tready (xb_to_ep0_tready ),
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.m_axis_chdr_tdata (ep0_to_xb_tdata ),
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.m_axis_chdr_tlast (ep0_to_xb_tlast ),
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.m_axis_chdr_tvalid (ep0_to_xb_tvalid ),
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.m_axis_chdr_tready (ep0_to_xb_tready ),
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.s_axis_data_tdata ({s_ep0_in0_tdata}),
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.s_axis_data_tlast ({s_ep0_in0_tlast}),
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.s_axis_data_tvalid ({s_ep0_in0_tvalid}),
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.s_axis_data_tready ({s_ep0_in0_tready}),
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.m_axis_data_tdata ({m_ep0_out0_tdata}),
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.m_axis_data_tlast ({m_ep0_out0_tlast}),
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.m_axis_data_tvalid ({m_ep0_out0_tvalid}),
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.m_axis_data_tready ({m_ep0_out0_tready}),
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.s_axis_ctrl_tdata (s_ep0_ctrl_tdata ),
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.s_axis_ctrl_tlast (s_ep0_ctrl_tlast ),
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.s_axis_ctrl_tvalid (s_ep0_ctrl_tvalid),
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.s_axis_ctrl_tready (s_ep0_ctrl_tready),
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.m_axis_ctrl_tdata (m_ep0_ctrl_tdata ),
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.m_axis_ctrl_tlast (m_ep0_ctrl_tlast ),
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.m_axis_ctrl_tvalid (m_ep0_ctrl_tvalid),
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.m_axis_ctrl_tready (m_ep0_ctrl_tready),
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.strm_seq_err_stb ( ),
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.strm_data_err_stb ( ),
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.strm_route_err_stb ( ),
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.signal_data_err (1'b0 )
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);
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wire [CHDR_W-1:0] m_ep1_out0_tdata;
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wire m_ep1_out0_tlast;
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wire m_ep1_out0_tvalid;
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wire m_ep1_out0_tready;
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wire [CHDR_W-1:0] s_ep1_in0_tdata;
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wire s_ep1_in0_tlast;
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wire s_ep1_in0_tvalid;
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wire s_ep1_in0_tready;
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wire [31:0] m_ep1_ctrl_tdata , s_ep1_ctrl_tdata ;
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wire m_ep1_ctrl_tlast , s_ep1_ctrl_tlast ;
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wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid;
|
|
wire m_ep1_ctrl_tready, s_ep1_ctrl_tready;
|
|
|
|
chdr_stream_endpoint #(
|
|
.PROTOVER (PROTOVER),
|
|
.CHDR_W (CHDR_W),
|
|
.AXIS_CTRL_EN (0),
|
|
.AXIS_DATA_EN (1),
|
|
.NUM_DATA_I (1),
|
|
.NUM_DATA_O (1),
|
|
.INST_NUM (1),
|
|
.CTRL_XBAR_PORT (2),
|
|
.INGRESS_BUFF_SIZE (15),
|
|
.MTU (MTU),
|
|
.REPORT_STRM_ERRS (1)
|
|
) ep1_i (
|
|
.rfnoc_chdr_clk (rfnoc_chdr_clk ),
|
|
.rfnoc_chdr_rst (rfnoc_chdr_rst ),
|
|
.rfnoc_ctrl_clk (rfnoc_ctrl_clk ),
|
|
.rfnoc_ctrl_rst (rfnoc_ctrl_rst ),
|
|
.device_id (device_id ),
|
|
.s_axis_chdr_tdata (xb_to_ep1_tdata ),
|
|
.s_axis_chdr_tlast (xb_to_ep1_tlast ),
|
|
.s_axis_chdr_tvalid (xb_to_ep1_tvalid ),
|
|
.s_axis_chdr_tready (xb_to_ep1_tready ),
|
|
.m_axis_chdr_tdata (ep1_to_xb_tdata ),
|
|
.m_axis_chdr_tlast (ep1_to_xb_tlast ),
|
|
.m_axis_chdr_tvalid (ep1_to_xb_tvalid ),
|
|
.m_axis_chdr_tready (ep1_to_xb_tready ),
|
|
.s_axis_data_tdata ({s_ep1_in0_tdata}),
|
|
.s_axis_data_tlast ({s_ep1_in0_tlast}),
|
|
.s_axis_data_tvalid ({s_ep1_in0_tvalid}),
|
|
.s_axis_data_tready ({s_ep1_in0_tready}),
|
|
.m_axis_data_tdata ({m_ep1_out0_tdata}),
|
|
.m_axis_data_tlast ({m_ep1_out0_tlast}),
|
|
.m_axis_data_tvalid ({m_ep1_out0_tvalid}),
|
|
.m_axis_data_tready ({m_ep1_out0_tready}),
|
|
.s_axis_ctrl_tdata (s_ep1_ctrl_tdata ),
|
|
.s_axis_ctrl_tlast (s_ep1_ctrl_tlast ),
|
|
.s_axis_ctrl_tvalid (s_ep1_ctrl_tvalid),
|
|
.s_axis_ctrl_tready (s_ep1_ctrl_tready),
|
|
.m_axis_ctrl_tdata (m_ep1_ctrl_tdata ),
|
|
.m_axis_ctrl_tlast (m_ep1_ctrl_tlast ),
|
|
.m_axis_ctrl_tvalid (m_ep1_ctrl_tvalid),
|
|
.m_axis_ctrl_tready (m_ep1_ctrl_tready),
|
|
.strm_seq_err_stb ( ),
|
|
.strm_data_err_stb ( ),
|
|
.strm_route_err_stb ( ),
|
|
.signal_data_err (1'b0 )
|
|
);
|
|
|
|
wire [CHDR_W-1:0] m_ep2_out0_tdata;
|
|
wire m_ep2_out0_tlast;
|
|
wire m_ep2_out0_tvalid;
|
|
wire m_ep2_out0_tready;
|
|
wire [CHDR_W-1:0] s_ep2_in0_tdata;
|
|
wire s_ep2_in0_tlast;
|
|
wire s_ep2_in0_tvalid;
|
|
wire s_ep2_in0_tready;
|
|
wire [31:0] m_ep2_ctrl_tdata , s_ep2_ctrl_tdata ;
|
|
wire m_ep2_ctrl_tlast , s_ep2_ctrl_tlast ;
|
|
wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid;
|
|
wire m_ep2_ctrl_tready, s_ep2_ctrl_tready;
|
|
|
|
chdr_stream_endpoint #(
|
|
.PROTOVER (PROTOVER),
|
|
.CHDR_W (CHDR_W),
|
|
.AXIS_CTRL_EN (0),
|
|
.AXIS_DATA_EN (1),
|
|
.NUM_DATA_I (1),
|
|
.NUM_DATA_O (1),
|
|
.INST_NUM (2),
|
|
.CTRL_XBAR_PORT (3),
|
|
.INGRESS_BUFF_SIZE (15),
|
|
.MTU (MTU),
|
|
.REPORT_STRM_ERRS (1)
|
|
) ep2_i (
|
|
.rfnoc_chdr_clk (rfnoc_chdr_clk ),
|
|
.rfnoc_chdr_rst (rfnoc_chdr_rst ),
|
|
.rfnoc_ctrl_clk (rfnoc_ctrl_clk ),
|
|
.rfnoc_ctrl_rst (rfnoc_ctrl_rst ),
|
|
.device_id (device_id ),
|
|
.s_axis_chdr_tdata (xb_to_ep2_tdata ),
|
|
.s_axis_chdr_tlast (xb_to_ep2_tlast ),
|
|
.s_axis_chdr_tvalid (xb_to_ep2_tvalid ),
|
|
.s_axis_chdr_tready (xb_to_ep2_tready ),
|
|
.m_axis_chdr_tdata (ep2_to_xb_tdata ),
|
|
.m_axis_chdr_tlast (ep2_to_xb_tlast ),
|
|
.m_axis_chdr_tvalid (ep2_to_xb_tvalid ),
|
|
.m_axis_chdr_tready (ep2_to_xb_tready ),
|
|
.s_axis_data_tdata ({s_ep2_in0_tdata}),
|
|
.s_axis_data_tlast ({s_ep2_in0_tlast}),
|
|
.s_axis_data_tvalid ({s_ep2_in0_tvalid}),
|
|
.s_axis_data_tready ({s_ep2_in0_tready}),
|
|
.m_axis_data_tdata ({m_ep2_out0_tdata}),
|
|
.m_axis_data_tlast ({m_ep2_out0_tlast}),
|
|
.m_axis_data_tvalid ({m_ep2_out0_tvalid}),
|
|
.m_axis_data_tready ({m_ep2_out0_tready}),
|
|
.s_axis_ctrl_tdata (s_ep2_ctrl_tdata ),
|
|
.s_axis_ctrl_tlast (s_ep2_ctrl_tlast ),
|
|
.s_axis_ctrl_tvalid (s_ep2_ctrl_tvalid),
|
|
.s_axis_ctrl_tready (s_ep2_ctrl_tready),
|
|
.m_axis_ctrl_tdata (m_ep2_ctrl_tdata ),
|
|
.m_axis_ctrl_tlast (m_ep2_ctrl_tlast ),
|
|
.m_axis_ctrl_tvalid (m_ep2_ctrl_tvalid),
|
|
.m_axis_ctrl_tready (m_ep2_ctrl_tready),
|
|
.strm_seq_err_stb ( ),
|
|
.strm_data_err_stb ( ),
|
|
.strm_route_err_stb ( ),
|
|
.signal_data_err (1'b0 )
|
|
);
|
|
|
|
wire [CHDR_W-1:0] m_ep3_out0_tdata;
|
|
wire m_ep3_out0_tlast;
|
|
wire m_ep3_out0_tvalid;
|
|
wire m_ep3_out0_tready;
|
|
wire [CHDR_W-1:0] s_ep3_in0_tdata;
|
|
wire s_ep3_in0_tlast;
|
|
wire s_ep3_in0_tvalid;
|
|
wire s_ep3_in0_tready;
|
|
wire [31:0] m_ep3_ctrl_tdata , s_ep3_ctrl_tdata ;
|
|
wire m_ep3_ctrl_tlast , s_ep3_ctrl_tlast ;
|
|
wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid;
|
|
wire m_ep3_ctrl_tready, s_ep3_ctrl_tready;
|
|
|
|
chdr_stream_endpoint #(
|
|
.PROTOVER (PROTOVER),
|
|
.CHDR_W (CHDR_W),
|
|
.AXIS_CTRL_EN (0),
|
|
.AXIS_DATA_EN (1),
|
|
.NUM_DATA_I (1),
|
|
.NUM_DATA_O (1),
|
|
.INST_NUM (3),
|
|
.CTRL_XBAR_PORT (4),
|
|
.INGRESS_BUFF_SIZE (15),
|
|
.MTU (MTU),
|
|
.REPORT_STRM_ERRS (1)
|
|
) ep3_i (
|
|
.rfnoc_chdr_clk (rfnoc_chdr_clk ),
|
|
.rfnoc_chdr_rst (rfnoc_chdr_rst ),
|
|
.rfnoc_ctrl_clk (rfnoc_ctrl_clk ),
|
|
.rfnoc_ctrl_rst (rfnoc_ctrl_rst ),
|
|
.device_id (device_id ),
|
|
.s_axis_chdr_tdata (xb_to_ep3_tdata ),
|
|
.s_axis_chdr_tlast (xb_to_ep3_tlast ),
|
|
.s_axis_chdr_tvalid (xb_to_ep3_tvalid ),
|
|
.s_axis_chdr_tready (xb_to_ep3_tready ),
|
|
.m_axis_chdr_tdata (ep3_to_xb_tdata ),
|
|
.m_axis_chdr_tlast (ep3_to_xb_tlast ),
|
|
.m_axis_chdr_tvalid (ep3_to_xb_tvalid ),
|
|
.m_axis_chdr_tready (ep3_to_xb_tready ),
|
|
.s_axis_data_tdata ({s_ep3_in0_tdata}),
|
|
.s_axis_data_tlast ({s_ep3_in0_tlast}),
|
|
.s_axis_data_tvalid ({s_ep3_in0_tvalid}),
|
|
.s_axis_data_tready ({s_ep3_in0_tready}),
|
|
.m_axis_data_tdata ({m_ep3_out0_tdata}),
|
|
.m_axis_data_tlast ({m_ep3_out0_tlast}),
|
|
.m_axis_data_tvalid ({m_ep3_out0_tvalid}),
|
|
.m_axis_data_tready ({m_ep3_out0_tready}),
|
|
.s_axis_ctrl_tdata (s_ep3_ctrl_tdata ),
|
|
.s_axis_ctrl_tlast (s_ep3_ctrl_tlast ),
|
|
.s_axis_ctrl_tvalid (s_ep3_ctrl_tvalid),
|
|
.s_axis_ctrl_tready (s_ep3_ctrl_tready),
|
|
.m_axis_ctrl_tdata (m_ep3_ctrl_tdata ),
|
|
.m_axis_ctrl_tlast (m_ep3_ctrl_tlast ),
|
|
.m_axis_ctrl_tvalid (m_ep3_ctrl_tvalid),
|
|
.m_axis_ctrl_tready (m_ep3_ctrl_tready),
|
|
.strm_seq_err_stb ( ),
|
|
.strm_data_err_stb ( ),
|
|
.strm_route_err_stb ( ),
|
|
.signal_data_err (1'b0 )
|
|
);
|
|
|
|
|
|
|
|
// ----------------------------------------------------
|
|
// Control Crossbar
|
|
// ----------------------------------------------------
|
|
|
|
wire [31:0] m_core_ctrl_tdata , s_core_ctrl_tdata ;
|
|
wire m_core_ctrl_tlast , s_core_ctrl_tlast ;
|
|
wire m_core_ctrl_tvalid, s_core_ctrl_tvalid;
|
|
wire m_core_ctrl_tready, s_core_ctrl_tready;
|
|
wire [31:0] m_duc0_ctrl_tdata , s_duc0_ctrl_tdata ;
|
|
wire m_duc0_ctrl_tlast , s_duc0_ctrl_tlast ;
|
|
wire m_duc0_ctrl_tvalid, s_duc0_ctrl_tvalid;
|
|
wire m_duc0_ctrl_tready, s_duc0_ctrl_tready;
|
|
wire [31:0] m_ddc0_ctrl_tdata , s_ddc0_ctrl_tdata ;
|
|
wire m_ddc0_ctrl_tlast , s_ddc0_ctrl_tlast ;
|
|
wire m_ddc0_ctrl_tvalid, s_ddc0_ctrl_tvalid;
|
|
wire m_ddc0_ctrl_tready, s_ddc0_ctrl_tready;
|
|
wire [31:0] m_radio0_ctrl_tdata , s_radio0_ctrl_tdata ;
|
|
wire m_radio0_ctrl_tlast , s_radio0_ctrl_tlast ;
|
|
wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid;
|
|
wire m_radio0_ctrl_tready, s_radio0_ctrl_tready;
|
|
wire [31:0] m_duc1_ctrl_tdata , s_duc1_ctrl_tdata ;
|
|
wire m_duc1_ctrl_tlast , s_duc1_ctrl_tlast ;
|
|
wire m_duc1_ctrl_tvalid, s_duc1_ctrl_tvalid;
|
|
wire m_duc1_ctrl_tready, s_duc1_ctrl_tready;
|
|
wire [31:0] m_ddc1_ctrl_tdata , s_ddc1_ctrl_tdata ;
|
|
wire m_ddc1_ctrl_tlast , s_ddc1_ctrl_tlast ;
|
|
wire m_ddc1_ctrl_tvalid, s_ddc1_ctrl_tvalid;
|
|
wire m_ddc1_ctrl_tready, s_ddc1_ctrl_tready;
|
|
wire [31:0] m_radio1_ctrl_tdata , s_radio1_ctrl_tdata ;
|
|
wire m_radio1_ctrl_tlast , s_radio1_ctrl_tlast ;
|
|
wire m_radio1_ctrl_tvalid, s_radio1_ctrl_tvalid;
|
|
wire m_radio1_ctrl_tready, s_radio1_ctrl_tready;
|
|
|
|
axis_ctrl_crossbar_nxn #(
|
|
.WIDTH (32),
|
|
.NPORTS (8),
|
|
.TOPOLOGY ("TORUS"),
|
|
.INGRESS_BUFF_SIZE(5),
|
|
.ROUTER_BUFF_SIZE (5),
|
|
.ROUTING_ALLOC ("WORMHOLE"),
|
|
.SWITCH_ALLOC ("PRIO")
|
|
) ctrl_xb_i (
|
|
.clk (rfnoc_ctrl_clk),
|
|
.reset (rfnoc_ctrl_rst),
|
|
.s_axis_tdata ({m_radio1_ctrl_tdata , m_ddc1_ctrl_tdata , m_duc1_ctrl_tdata , m_radio0_ctrl_tdata , m_ddc0_ctrl_tdata , m_duc0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }),
|
|
.s_axis_tvalid ({m_radio1_ctrl_tvalid, m_ddc1_ctrl_tvalid, m_duc1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ddc0_ctrl_tvalid, m_duc0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}),
|
|
.s_axis_tlast ({m_radio1_ctrl_tlast , m_ddc1_ctrl_tlast , m_duc1_ctrl_tlast , m_radio0_ctrl_tlast , m_ddc0_ctrl_tlast , m_duc0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }),
|
|
.s_axis_tready ({m_radio1_ctrl_tready, m_ddc1_ctrl_tready, m_duc1_ctrl_tready, m_radio0_ctrl_tready, m_ddc0_ctrl_tready, m_duc0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}),
|
|
.m_axis_tdata ({s_radio1_ctrl_tdata , s_ddc1_ctrl_tdata , s_duc1_ctrl_tdata , s_radio0_ctrl_tdata , s_ddc0_ctrl_tdata , s_duc0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }),
|
|
.m_axis_tvalid ({s_radio1_ctrl_tvalid, s_ddc1_ctrl_tvalid, s_duc1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ddc0_ctrl_tvalid, s_duc0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}),
|
|
.m_axis_tlast ({s_radio1_ctrl_tlast , s_ddc1_ctrl_tlast , s_duc1_ctrl_tlast , s_radio0_ctrl_tlast , s_ddc0_ctrl_tlast , s_duc0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }),
|
|
.m_axis_tready ({s_radio1_ctrl_tready, s_ddc1_ctrl_tready, s_duc1_ctrl_tready, s_radio0_ctrl_tready, s_ddc0_ctrl_tready, s_duc0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}),
|
|
.deadlock_detected()
|
|
);
|
|
|
|
// ----------------------------------------------------
|
|
// RFNoC Core Kernel
|
|
// ----------------------------------------------------
|
|
wire [(512*6)-1:0] rfnoc_core_config, rfnoc_core_status;
|
|
|
|
rfnoc_core_kernel #(
|
|
.PROTOVER (PROTOVER),
|
|
.DEVICE_TYPE (16'h1300),
|
|
.DEVICE_FAMILY ("7SERIES"),
|
|
.SAFE_START_CLKS (0),
|
|
.NUM_BLOCKS (6),
|
|
.NUM_STREAM_ENDPOINTS(4),
|
|
.NUM_ENDPOINTS_CTRL (1),
|
|
.NUM_TRANSPORTS (3),
|
|
.NUM_EDGES (16),
|
|
.CHDR_XBAR_PRESENT (1),
|
|
.EDGE_TBL_FILE (EDGE_TBL_FILE)
|
|
) core_kernel_i (
|
|
.chdr_aclk (chdr_aclk),
|
|
.chdr_aclk_locked (1'b1),
|
|
.ctrl_aclk (ctrl_aclk),
|
|
.ctrl_aclk_locked (1'b1),
|
|
.core_arst (core_arst),
|
|
.core_chdr_clk (rfnoc_chdr_clk),
|
|
.core_chdr_rst (rfnoc_chdr_rst),
|
|
.core_ctrl_clk (rfnoc_ctrl_clk),
|
|
.core_ctrl_rst (rfnoc_ctrl_rst),
|
|
.s_axis_ctrl_tdata (s_core_ctrl_tdata ),
|
|
.s_axis_ctrl_tlast (s_core_ctrl_tlast ),
|
|
.s_axis_ctrl_tvalid (s_core_ctrl_tvalid),
|
|
.s_axis_ctrl_tready (s_core_ctrl_tready),
|
|
.m_axis_ctrl_tdata (m_core_ctrl_tdata ),
|
|
.m_axis_ctrl_tlast (m_core_ctrl_tlast ),
|
|
.m_axis_ctrl_tvalid (m_core_ctrl_tvalid),
|
|
.m_axis_ctrl_tready (m_core_ctrl_tready),
|
|
.device_id (device_id),
|
|
.rfnoc_core_config (rfnoc_core_config),
|
|
.rfnoc_core_status (rfnoc_core_status)
|
|
);
|
|
|
|
// ----------------------------------------------------
|
|
// Blocks
|
|
// ----------------------------------------------------
|
|
|
|
// ----------------------------------------------------
|
|
// duc0
|
|
// ----------------------------------------------------
|
|
wire duc0_ce_clk;
|
|
wire [CHDR_W-1:0] s_duc0_in_1_tdata , s_duc0_in_0_tdata ;
|
|
wire s_duc0_in_1_tlast , s_duc0_in_0_tlast ;
|
|
wire s_duc0_in_1_tvalid, s_duc0_in_0_tvalid;
|
|
wire s_duc0_in_1_tready, s_duc0_in_0_tready;
|
|
wire [CHDR_W-1:0] m_duc0_out_1_tdata , m_duc0_out_0_tdata ;
|
|
wire m_duc0_out_1_tlast , m_duc0_out_0_tlast ;
|
|
wire m_duc0_out_1_tvalid, m_duc0_out_0_tvalid;
|
|
wire m_duc0_out_1_tready, m_duc0_out_0_tready;
|
|
|
|
|
|
rfnoc_block_duc #(
|
|
.THIS_PORTID(2),
|
|
.CHDR_W(CHDR_W),
|
|
.NUM_PORTS(2),
|
|
.NUM_HB(3),
|
|
.CIC_MAX_INTERP(255),
|
|
.MTU(MTU)
|
|
) b_duc0_0 (
|
|
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
|
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
|
.ce_clk(duc0_ce_clk),
|
|
.rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]),
|
|
.rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]),
|
|
|
|
|
|
.s_rfnoc_chdr_tdata ({s_duc0_in_1_tdata , s_duc0_in_0_tdata }),
|
|
.s_rfnoc_chdr_tlast ({s_duc0_in_1_tlast , s_duc0_in_0_tlast }),
|
|
.s_rfnoc_chdr_tvalid({s_duc0_in_1_tvalid, s_duc0_in_0_tvalid}),
|
|
.s_rfnoc_chdr_tready({s_duc0_in_1_tready, s_duc0_in_0_tready}),
|
|
.m_rfnoc_chdr_tdata ({m_duc0_out_1_tdata , m_duc0_out_0_tdata }),
|
|
.m_rfnoc_chdr_tlast ({m_duc0_out_1_tlast , m_duc0_out_0_tlast }),
|
|
.m_rfnoc_chdr_tvalid({m_duc0_out_1_tvalid, m_duc0_out_0_tvalid}),
|
|
.m_rfnoc_chdr_tready({m_duc0_out_1_tready, m_duc0_out_0_tready}),
|
|
.s_rfnoc_ctrl_tdata (s_duc0_ctrl_tdata ),
|
|
.s_rfnoc_ctrl_tlast (s_duc0_ctrl_tlast ),
|
|
.s_rfnoc_ctrl_tvalid(s_duc0_ctrl_tvalid),
|
|
.s_rfnoc_ctrl_tready(s_duc0_ctrl_tready),
|
|
.m_rfnoc_ctrl_tdata (m_duc0_ctrl_tdata ),
|
|
.m_rfnoc_ctrl_tlast (m_duc0_ctrl_tlast ),
|
|
.m_rfnoc_ctrl_tvalid(m_duc0_ctrl_tvalid),
|
|
.m_rfnoc_ctrl_tready(m_duc0_ctrl_tready)
|
|
);
|
|
|
|
|
|
// ----------------------------------------------------
|
|
// ddc0
|
|
// ----------------------------------------------------
|
|
wire ddc0_ce_clk;
|
|
wire [CHDR_W-1:0] s_ddc0_in_1_tdata , s_ddc0_in_0_tdata ;
|
|
wire s_ddc0_in_1_tlast , s_ddc0_in_0_tlast ;
|
|
wire s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid;
|
|
wire s_ddc0_in_1_tready, s_ddc0_in_0_tready;
|
|
wire [CHDR_W-1:0] m_ddc0_out_1_tdata , m_ddc0_out_0_tdata ;
|
|
wire m_ddc0_out_1_tlast , m_ddc0_out_0_tlast ;
|
|
wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid;
|
|
wire m_ddc0_out_1_tready, m_ddc0_out_0_tready;
|
|
|
|
|
|
rfnoc_block_ddc #(
|
|
.THIS_PORTID(3),
|
|
.CHDR_W(CHDR_W),
|
|
.NUM_PORTS(2),
|
|
.NUM_HB(3),
|
|
.CIC_MAX_DECIM(255),
|
|
.MTU(MTU)
|
|
) b_ddc0_1 (
|
|
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
|
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
|
.ce_clk(ddc0_ce_clk),
|
|
.rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]),
|
|
.rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]),
|
|
|
|
|
|
.s_rfnoc_chdr_tdata ({s_ddc0_in_1_tdata , s_ddc0_in_0_tdata }),
|
|
.s_rfnoc_chdr_tlast ({s_ddc0_in_1_tlast , s_ddc0_in_0_tlast }),
|
|
.s_rfnoc_chdr_tvalid({s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid}),
|
|
.s_rfnoc_chdr_tready({s_ddc0_in_1_tready, s_ddc0_in_0_tready}),
|
|
.m_rfnoc_chdr_tdata ({m_ddc0_out_1_tdata , m_ddc0_out_0_tdata }),
|
|
.m_rfnoc_chdr_tlast ({m_ddc0_out_1_tlast , m_ddc0_out_0_tlast }),
|
|
.m_rfnoc_chdr_tvalid({m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid}),
|
|
.m_rfnoc_chdr_tready({m_ddc0_out_1_tready, m_ddc0_out_0_tready}),
|
|
.s_rfnoc_ctrl_tdata (s_ddc0_ctrl_tdata ),
|
|
.s_rfnoc_ctrl_tlast (s_ddc0_ctrl_tlast ),
|
|
.s_rfnoc_ctrl_tvalid(s_ddc0_ctrl_tvalid),
|
|
.s_rfnoc_ctrl_tready(s_ddc0_ctrl_tready),
|
|
.m_rfnoc_ctrl_tdata (m_ddc0_ctrl_tdata ),
|
|
.m_rfnoc_ctrl_tlast (m_ddc0_ctrl_tlast ),
|
|
.m_rfnoc_ctrl_tvalid(m_ddc0_ctrl_tvalid),
|
|
.m_rfnoc_ctrl_tready(m_ddc0_ctrl_tready)
|
|
);
|
|
|
|
|
|
// ----------------------------------------------------
|
|
// radio0
|
|
// ----------------------------------------------------
|
|
wire radio0_radio_clk;
|
|
wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ;
|
|
wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ;
|
|
wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid;
|
|
wire s_radio0_in_1_tready, s_radio0_in_0_tready;
|
|
wire [CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ;
|
|
wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ;
|
|
wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
|
|
wire m_radio0_out_1_tready, m_radio0_out_0_tready;
|
|
|
|
// ctrl_port
|
|
wire [ 1-1:0] radio0_m_ctrlport_req_wr;
|
|
wire [ 1-1:0] radio0_m_ctrlport_req_rd;
|
|
wire [ 20-1:0] radio0_m_ctrlport_req_addr;
|
|
wire [ 32-1:0] radio0_m_ctrlport_req_data;
|
|
wire [ 4-1:0] radio0_m_ctrlport_req_byte_en;
|
|
wire [ 1-1:0] radio0_m_ctrlport_req_has_time;
|
|
wire [ 64-1:0] radio0_m_ctrlport_req_time;
|
|
wire [ 1-1:0] radio0_m_ctrlport_resp_ack;
|
|
wire [ 2-1:0] radio0_m_ctrlport_resp_status;
|
|
wire [ 32-1:0] radio0_m_ctrlport_resp_data;
|
|
// time_keeper
|
|
wire [ 64-1:0] radio0_radio_time;
|
|
// x300_radio
|
|
wire [ 64-1:0] radio0_radio_rx_data;
|
|
wire [ 2-1:0] radio0_radio_rx_stb;
|
|
wire [ 2-1:0] radio0_radio_rx_running;
|
|
wire [ 64-1:0] radio0_radio_tx_data;
|
|
wire [ 2-1:0] radio0_radio_tx_stb;
|
|
wire [ 2-1:0] radio0_radio_tx_running;
|
|
|
|
rfnoc_block_radio #(
|
|
.THIS_PORTID(4),
|
|
.CHDR_W(CHDR_W),
|
|
.NUM_PORTS(2),
|
|
.MTU(MTU)
|
|
) b_radio0_2 (
|
|
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
|
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
|
.radio_clk(radio0_radio_clk),
|
|
.rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]),
|
|
.rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]),
|
|
|
|
.m_ctrlport_req_wr(radio0_m_ctrlport_req_wr),
|
|
.m_ctrlport_req_rd(radio0_m_ctrlport_req_rd),
|
|
.m_ctrlport_req_addr(radio0_m_ctrlport_req_addr),
|
|
.m_ctrlport_req_data(radio0_m_ctrlport_req_data),
|
|
.m_ctrlport_req_byte_en(radio0_m_ctrlport_req_byte_en),
|
|
.m_ctrlport_req_has_time(radio0_m_ctrlport_req_has_time),
|
|
.m_ctrlport_req_time(radio0_m_ctrlport_req_time),
|
|
.m_ctrlport_resp_ack(radio0_m_ctrlport_resp_ack),
|
|
.m_ctrlport_resp_status(radio0_m_ctrlport_resp_status),
|
|
.m_ctrlport_resp_data(radio0_m_ctrlport_resp_data),
|
|
.radio_time(radio0_radio_time),
|
|
.radio_rx_data(radio0_radio_rx_data),
|
|
.radio_rx_stb(radio0_radio_rx_stb),
|
|
.radio_rx_running(radio0_radio_rx_running),
|
|
.radio_tx_data(radio0_radio_tx_data),
|
|
.radio_tx_stb(radio0_radio_tx_stb),
|
|
.radio_tx_running(radio0_radio_tx_running),
|
|
|
|
.s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }),
|
|
.s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }),
|
|
.s_rfnoc_chdr_tvalid({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}),
|
|
.s_rfnoc_chdr_tready({s_radio0_in_1_tready, s_radio0_in_0_tready}),
|
|
.m_rfnoc_chdr_tdata ({m_radio0_out_1_tdata , m_radio0_out_0_tdata }),
|
|
.m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }),
|
|
.m_rfnoc_chdr_tvalid({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}),
|
|
.m_rfnoc_chdr_tready({m_radio0_out_1_tready, m_radio0_out_0_tready}),
|
|
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ),
|
|
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ),
|
|
.s_rfnoc_ctrl_tvalid(s_radio0_ctrl_tvalid),
|
|
.s_rfnoc_ctrl_tready(s_radio0_ctrl_tready),
|
|
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ),
|
|
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ),
|
|
.m_rfnoc_ctrl_tvalid(m_radio0_ctrl_tvalid),
|
|
.m_rfnoc_ctrl_tready(m_radio0_ctrl_tready)
|
|
);
|
|
|
|
|
|
// ----------------------------------------------------
|
|
// duc1
|
|
// ----------------------------------------------------
|
|
wire duc1_ce_clk;
|
|
wire [CHDR_W-1:0] s_duc1_in_1_tdata , s_duc1_in_0_tdata ;
|
|
wire s_duc1_in_1_tlast , s_duc1_in_0_tlast ;
|
|
wire s_duc1_in_1_tvalid, s_duc1_in_0_tvalid;
|
|
wire s_duc1_in_1_tready, s_duc1_in_0_tready;
|
|
wire [CHDR_W-1:0] m_duc1_out_1_tdata , m_duc1_out_0_tdata ;
|
|
wire m_duc1_out_1_tlast , m_duc1_out_0_tlast ;
|
|
wire m_duc1_out_1_tvalid, m_duc1_out_0_tvalid;
|
|
wire m_duc1_out_1_tready, m_duc1_out_0_tready;
|
|
|
|
|
|
rfnoc_block_duc #(
|
|
.THIS_PORTID(5),
|
|
.CHDR_W(CHDR_W),
|
|
.NUM_PORTS(2),
|
|
.NUM_HB(3),
|
|
.CIC_MAX_INTERP(255),
|
|
.MTU(MTU)
|
|
) b_duc1_3 (
|
|
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
|
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
|
.ce_clk(duc1_ce_clk),
|
|
.rfnoc_core_config (rfnoc_core_config[512*4-1:512*3]),
|
|
.rfnoc_core_status (rfnoc_core_status[512*4-1:512*3]),
|
|
|
|
|
|
.s_rfnoc_chdr_tdata ({s_duc1_in_1_tdata , s_duc1_in_0_tdata }),
|
|
.s_rfnoc_chdr_tlast ({s_duc1_in_1_tlast , s_duc1_in_0_tlast }),
|
|
.s_rfnoc_chdr_tvalid({s_duc1_in_1_tvalid, s_duc1_in_0_tvalid}),
|
|
.s_rfnoc_chdr_tready({s_duc1_in_1_tready, s_duc1_in_0_tready}),
|
|
.m_rfnoc_chdr_tdata ({m_duc1_out_1_tdata , m_duc1_out_0_tdata }),
|
|
.m_rfnoc_chdr_tlast ({m_duc1_out_1_tlast , m_duc1_out_0_tlast }),
|
|
.m_rfnoc_chdr_tvalid({m_duc1_out_1_tvalid, m_duc1_out_0_tvalid}),
|
|
.m_rfnoc_chdr_tready({m_duc1_out_1_tready, m_duc1_out_0_tready}),
|
|
.s_rfnoc_ctrl_tdata (s_duc1_ctrl_tdata ),
|
|
.s_rfnoc_ctrl_tlast (s_duc1_ctrl_tlast ),
|
|
.s_rfnoc_ctrl_tvalid(s_duc1_ctrl_tvalid),
|
|
.s_rfnoc_ctrl_tready(s_duc1_ctrl_tready),
|
|
.m_rfnoc_ctrl_tdata (m_duc1_ctrl_tdata ),
|
|
.m_rfnoc_ctrl_tlast (m_duc1_ctrl_tlast ),
|
|
.m_rfnoc_ctrl_tvalid(m_duc1_ctrl_tvalid),
|
|
.m_rfnoc_ctrl_tready(m_duc1_ctrl_tready)
|
|
);
|
|
|
|
|
|
// ----------------------------------------------------
|
|
// ddc1
|
|
// ----------------------------------------------------
|
|
wire ddc1_ce_clk;
|
|
wire [CHDR_W-1:0] s_ddc1_in_1_tdata , s_ddc1_in_0_tdata ;
|
|
wire s_ddc1_in_1_tlast , s_ddc1_in_0_tlast ;
|
|
wire s_ddc1_in_1_tvalid, s_ddc1_in_0_tvalid;
|
|
wire s_ddc1_in_1_tready, s_ddc1_in_0_tready;
|
|
wire [CHDR_W-1:0] m_ddc1_out_1_tdata , m_ddc1_out_0_tdata ;
|
|
wire m_ddc1_out_1_tlast , m_ddc1_out_0_tlast ;
|
|
wire m_ddc1_out_1_tvalid, m_ddc1_out_0_tvalid;
|
|
wire m_ddc1_out_1_tready, m_ddc1_out_0_tready;
|
|
|
|
|
|
rfnoc_block_ddc #(
|
|
.THIS_PORTID(6),
|
|
.CHDR_W(CHDR_W),
|
|
.NUM_PORTS(2),
|
|
.NUM_HB(3),
|
|
.CIC_MAX_DECIM(255),
|
|
.MTU(MTU)
|
|
) b_ddc1_4 (
|
|
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
|
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
|
.ce_clk(ddc1_ce_clk),
|
|
.rfnoc_core_config (rfnoc_core_config[512*5-1:512*4]),
|
|
.rfnoc_core_status (rfnoc_core_status[512*5-1:512*4]),
|
|
|
|
|
|
.s_rfnoc_chdr_tdata ({s_ddc1_in_1_tdata , s_ddc1_in_0_tdata }),
|
|
.s_rfnoc_chdr_tlast ({s_ddc1_in_1_tlast , s_ddc1_in_0_tlast }),
|
|
.s_rfnoc_chdr_tvalid({s_ddc1_in_1_tvalid, s_ddc1_in_0_tvalid}),
|
|
.s_rfnoc_chdr_tready({s_ddc1_in_1_tready, s_ddc1_in_0_tready}),
|
|
.m_rfnoc_chdr_tdata ({m_ddc1_out_1_tdata , m_ddc1_out_0_tdata }),
|
|
.m_rfnoc_chdr_tlast ({m_ddc1_out_1_tlast , m_ddc1_out_0_tlast }),
|
|
.m_rfnoc_chdr_tvalid({m_ddc1_out_1_tvalid, m_ddc1_out_0_tvalid}),
|
|
.m_rfnoc_chdr_tready({m_ddc1_out_1_tready, m_ddc1_out_0_tready}),
|
|
.s_rfnoc_ctrl_tdata (s_ddc1_ctrl_tdata ),
|
|
.s_rfnoc_ctrl_tlast (s_ddc1_ctrl_tlast ),
|
|
.s_rfnoc_ctrl_tvalid(s_ddc1_ctrl_tvalid),
|
|
.s_rfnoc_ctrl_tready(s_ddc1_ctrl_tready),
|
|
.m_rfnoc_ctrl_tdata (m_ddc1_ctrl_tdata ),
|
|
.m_rfnoc_ctrl_tlast (m_ddc1_ctrl_tlast ),
|
|
.m_rfnoc_ctrl_tvalid(m_ddc1_ctrl_tvalid),
|
|
.m_rfnoc_ctrl_tready(m_ddc1_ctrl_tready)
|
|
);
|
|
|
|
|
|
// ----------------------------------------------------
|
|
// radio1
|
|
// ----------------------------------------------------
|
|
wire radio1_radio_clk;
|
|
wire [CHDR_W-1:0] s_radio1_in_1_tdata , s_radio1_in_0_tdata ;
|
|
wire s_radio1_in_1_tlast , s_radio1_in_0_tlast ;
|
|
wire s_radio1_in_1_tvalid, s_radio1_in_0_tvalid;
|
|
wire s_radio1_in_1_tready, s_radio1_in_0_tready;
|
|
wire [CHDR_W-1:0] m_radio1_out_1_tdata , m_radio1_out_0_tdata ;
|
|
wire m_radio1_out_1_tlast , m_radio1_out_0_tlast ;
|
|
wire m_radio1_out_1_tvalid, m_radio1_out_0_tvalid;
|
|
wire m_radio1_out_1_tready, m_radio1_out_0_tready;
|
|
|
|
// ctrl_port
|
|
wire [ 1-1:0] radio1_m_ctrlport_req_wr;
|
|
wire [ 1-1:0] radio1_m_ctrlport_req_rd;
|
|
wire [ 20-1:0] radio1_m_ctrlport_req_addr;
|
|
wire [ 32-1:0] radio1_m_ctrlport_req_data;
|
|
wire [ 4-1:0] radio1_m_ctrlport_req_byte_en;
|
|
wire [ 1-1:0] radio1_m_ctrlport_req_has_time;
|
|
wire [ 64-1:0] radio1_m_ctrlport_req_time;
|
|
wire [ 1-1:0] radio1_m_ctrlport_resp_ack;
|
|
wire [ 2-1:0] radio1_m_ctrlport_resp_status;
|
|
wire [ 32-1:0] radio1_m_ctrlport_resp_data;
|
|
// time_keeper
|
|
wire [ 64-1:0] radio1_radio_time;
|
|
// x300_radio
|
|
wire [ 64-1:0] radio1_radio_rx_data;
|
|
wire [ 2-1:0] radio1_radio_rx_stb;
|
|
wire [ 2-1:0] radio1_radio_rx_running;
|
|
wire [ 64-1:0] radio1_radio_tx_data;
|
|
wire [ 2-1:0] radio1_radio_tx_stb;
|
|
wire [ 2-1:0] radio1_radio_tx_running;
|
|
|
|
rfnoc_block_radio #(
|
|
.THIS_PORTID(7),
|
|
.CHDR_W(CHDR_W),
|
|
.NUM_PORTS(2),
|
|
.MTU(MTU)
|
|
) b_radio1_5 (
|
|
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
|
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
|
.radio_clk(radio1_radio_clk),
|
|
.rfnoc_core_config (rfnoc_core_config[512*6-1:512*5]),
|
|
.rfnoc_core_status (rfnoc_core_status[512*6-1:512*5]),
|
|
|
|
.m_ctrlport_req_wr(radio1_m_ctrlport_req_wr),
|
|
.m_ctrlport_req_rd(radio1_m_ctrlport_req_rd),
|
|
.m_ctrlport_req_addr(radio1_m_ctrlport_req_addr),
|
|
.m_ctrlport_req_data(radio1_m_ctrlport_req_data),
|
|
.m_ctrlport_req_byte_en(radio1_m_ctrlport_req_byte_en),
|
|
.m_ctrlport_req_has_time(radio1_m_ctrlport_req_has_time),
|
|
.m_ctrlport_req_time(radio1_m_ctrlport_req_time),
|
|
.m_ctrlport_resp_ack(radio1_m_ctrlport_resp_ack),
|
|
.m_ctrlport_resp_status(radio1_m_ctrlport_resp_status),
|
|
.m_ctrlport_resp_data(radio1_m_ctrlport_resp_data),
|
|
.radio_time(radio1_radio_time),
|
|
.radio_rx_data(radio1_radio_rx_data),
|
|
.radio_rx_stb(radio1_radio_rx_stb),
|
|
.radio_rx_running(radio1_radio_rx_running),
|
|
.radio_tx_data(radio1_radio_tx_data),
|
|
.radio_tx_stb(radio1_radio_tx_stb),
|
|
.radio_tx_running(radio1_radio_tx_running),
|
|
|
|
.s_rfnoc_chdr_tdata ({s_radio1_in_1_tdata , s_radio1_in_0_tdata }),
|
|
.s_rfnoc_chdr_tlast ({s_radio1_in_1_tlast , s_radio1_in_0_tlast }),
|
|
.s_rfnoc_chdr_tvalid({s_radio1_in_1_tvalid, s_radio1_in_0_tvalid}),
|
|
.s_rfnoc_chdr_tready({s_radio1_in_1_tready, s_radio1_in_0_tready}),
|
|
.m_rfnoc_chdr_tdata ({m_radio1_out_1_tdata , m_radio1_out_0_tdata }),
|
|
.m_rfnoc_chdr_tlast ({m_radio1_out_1_tlast , m_radio1_out_0_tlast }),
|
|
.m_rfnoc_chdr_tvalid({m_radio1_out_1_tvalid, m_radio1_out_0_tvalid}),
|
|
.m_rfnoc_chdr_tready({m_radio1_out_1_tready, m_radio1_out_0_tready}),
|
|
.s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata ),
|
|
.s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast ),
|
|
.s_rfnoc_ctrl_tvalid(s_radio1_ctrl_tvalid),
|
|
.s_rfnoc_ctrl_tready(s_radio1_ctrl_tready),
|
|
.m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata ),
|
|
.m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast ),
|
|
.m_rfnoc_ctrl_tvalid(m_radio1_ctrl_tvalid),
|
|
.m_rfnoc_ctrl_tready(m_radio1_ctrl_tready)
|
|
);
|
|
|
|
|
|
// ----------------------------------------------------
|
|
// Static Router
|
|
// ----------------------------------------------------
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assign s_duc0_in_0_tdata = m_ep0_out0_tdata ;
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assign s_duc0_in_0_tlast = m_ep0_out0_tlast ;
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assign s_duc0_in_0_tvalid = m_ep0_out0_tvalid;
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assign m_ep0_out0_tready = s_duc0_in_0_tready;
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assign s_radio0_in_0_tdata = m_duc0_out_0_tdata ;
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assign s_radio0_in_0_tlast = m_duc0_out_0_tlast ;
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assign s_radio0_in_0_tvalid = m_duc0_out_0_tvalid;
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assign m_duc0_out_0_tready = s_radio0_in_0_tready;
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assign s_ddc0_in_0_tdata = m_radio0_out_0_tdata ;
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assign s_ddc0_in_0_tlast = m_radio0_out_0_tlast ;
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assign s_ddc0_in_0_tvalid = m_radio0_out_0_tvalid;
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assign m_radio0_out_0_tready = s_ddc0_in_0_tready;
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assign s_ep0_in0_tdata = m_ddc0_out_0_tdata ;
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assign s_ep0_in0_tlast = m_ddc0_out_0_tlast ;
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assign s_ep0_in0_tvalid = m_ddc0_out_0_tvalid;
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assign m_ddc0_out_0_tready = s_ep0_in0_tready;
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assign s_duc0_in_1_tdata = m_ep1_out0_tdata ;
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assign s_duc0_in_1_tlast = m_ep1_out0_tlast ;
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assign s_duc0_in_1_tvalid = m_ep1_out0_tvalid;
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assign m_ep1_out0_tready = s_duc0_in_1_tready;
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assign s_radio0_in_1_tdata = m_duc0_out_1_tdata ;
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assign s_radio0_in_1_tlast = m_duc0_out_1_tlast ;
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assign s_radio0_in_1_tvalid = m_duc0_out_1_tvalid;
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assign m_duc0_out_1_tready = s_radio0_in_1_tready;
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assign s_ddc0_in_1_tdata = m_radio0_out_1_tdata ;
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assign s_ddc0_in_1_tlast = m_radio0_out_1_tlast ;
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assign s_ddc0_in_1_tvalid = m_radio0_out_1_tvalid;
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assign m_radio0_out_1_tready = s_ddc0_in_1_tready;
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assign s_ep1_in0_tdata = m_ddc0_out_1_tdata ;
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assign s_ep1_in0_tlast = m_ddc0_out_1_tlast ;
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assign s_ep1_in0_tvalid = m_ddc0_out_1_tvalid;
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assign m_ddc0_out_1_tready = s_ep1_in0_tready;
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assign s_duc1_in_0_tdata = m_ep2_out0_tdata ;
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assign s_duc1_in_0_tlast = m_ep2_out0_tlast ;
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assign s_duc1_in_0_tvalid = m_ep2_out0_tvalid;
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assign m_ep2_out0_tready = s_duc1_in_0_tready;
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assign s_radio1_in_0_tdata = m_duc1_out_0_tdata ;
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assign s_radio1_in_0_tlast = m_duc1_out_0_tlast ;
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assign s_radio1_in_0_tvalid = m_duc1_out_0_tvalid;
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assign m_duc1_out_0_tready = s_radio1_in_0_tready;
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assign s_ddc1_in_0_tdata = m_radio1_out_0_tdata ;
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assign s_ddc1_in_0_tlast = m_radio1_out_0_tlast ;
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assign s_ddc1_in_0_tvalid = m_radio1_out_0_tvalid;
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assign m_radio1_out_0_tready = s_ddc1_in_0_tready;
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assign s_ep2_in0_tdata = m_ddc1_out_0_tdata ;
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assign s_ep2_in0_tlast = m_ddc1_out_0_tlast ;
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assign s_ep2_in0_tvalid = m_ddc1_out_0_tvalid;
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assign m_ddc1_out_0_tready = s_ep2_in0_tready;
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assign s_duc1_in_1_tdata = m_ep3_out0_tdata ;
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assign s_duc1_in_1_tlast = m_ep3_out0_tlast ;
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assign s_duc1_in_1_tvalid = m_ep3_out0_tvalid;
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assign m_ep3_out0_tready = s_duc1_in_1_tready;
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assign s_radio1_in_1_tdata = m_duc1_out_1_tdata ;
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assign s_radio1_in_1_tlast = m_duc1_out_1_tlast ;
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assign s_radio1_in_1_tvalid = m_duc1_out_1_tvalid;
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assign m_duc1_out_1_tready = s_radio1_in_1_tready;
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assign s_ddc1_in_1_tdata = m_radio1_out_1_tdata ;
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assign s_ddc1_in_1_tlast = m_radio1_out_1_tlast ;
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assign s_ddc1_in_1_tvalid = m_radio1_out_1_tvalid;
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assign m_radio1_out_1_tready = s_ddc1_in_1_tready;
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assign s_ep3_in0_tdata = m_ddc1_out_1_tdata ;
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assign s_ep3_in0_tlast = m_ddc1_out_1_tlast ;
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assign s_ep3_in0_tvalid = m_ddc1_out_1_tvalid;
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assign m_ddc1_out_1_tready = s_ep3_in0_tready;
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// ----------------------------------------------------
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// Unused Ports
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// ----------------------------------------------------
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// ----------------------------------------------------
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// Clock Domains
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// ----------------------------------------------------
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assign radio0_radio_clk = radio_clk;
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assign ddc0_ce_clk = rfnoc_chdr_clk;
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assign duc0_ce_clk = rfnoc_chdr_clk;
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assign radio1_radio_clk = radio_clk;
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assign ddc1_ce_clk = rfnoc_chdr_clk;
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assign duc1_ce_clk = rfnoc_chdr_clk;
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// ----------------------------------------------------
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// IO Port Connection
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// ----------------------------------------------------
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// Master/Slave Connections:
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assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr;
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assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd;
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assign m_ctrlport_radio0_req_addr = radio0_m_ctrlport_req_addr;
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assign m_ctrlport_radio0_req_data = radio0_m_ctrlport_req_data;
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assign m_ctrlport_radio0_req_byte_en = radio0_m_ctrlport_req_byte_en;
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assign m_ctrlport_radio0_req_has_time = radio0_m_ctrlport_req_has_time;
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assign m_ctrlport_radio0_req_time = radio0_m_ctrlport_req_time;
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assign radio0_m_ctrlport_resp_ack = m_ctrlport_radio0_resp_ack;
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assign radio0_m_ctrlport_resp_status = m_ctrlport_radio0_resp_status;
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assign radio0_m_ctrlport_resp_data = m_ctrlport_radio0_resp_data;
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assign m_ctrlport_radio1_req_wr = radio1_m_ctrlport_req_wr;
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assign m_ctrlport_radio1_req_rd = radio1_m_ctrlport_req_rd;
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assign m_ctrlport_radio1_req_addr = radio1_m_ctrlport_req_addr;
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assign m_ctrlport_radio1_req_data = radio1_m_ctrlport_req_data;
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assign m_ctrlport_radio1_req_byte_en = radio1_m_ctrlport_req_byte_en;
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assign m_ctrlport_radio1_req_has_time = radio1_m_ctrlport_req_has_time;
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assign m_ctrlport_radio1_req_time = radio1_m_ctrlport_req_time;
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assign radio1_m_ctrlport_resp_ack = m_ctrlport_radio1_resp_ack;
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assign radio1_m_ctrlport_resp_status = m_ctrlport_radio1_resp_status;
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assign radio1_m_ctrlport_resp_data = m_ctrlport_radio1_resp_data;
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assign radio0_radio_rx_data = radio_rx_data_radio0;
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assign radio0_radio_rx_stb = radio_rx_stb_radio0;
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assign radio_rx_running_radio0 = radio0_radio_rx_running;
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assign radio_tx_data_radio0 = radio0_radio_tx_data;
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assign radio0_radio_tx_stb = radio_tx_stb_radio0;
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assign radio_tx_running_radio0 = radio0_radio_tx_running;
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|
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assign radio1_radio_rx_data = radio_rx_data_radio1;
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assign radio1_radio_rx_stb = radio_rx_stb_radio1;
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assign radio_rx_running_radio1 = radio1_radio_rx_running;
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assign radio_tx_data_radio1 = radio1_radio_tx_data;
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assign radio1_radio_tx_stb = radio_tx_stb_radio1;
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assign radio_tx_running_radio1 = radio1_radio_tx_running;
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|
|
// Broadcaster/Listener Connections:
|
|
assign radio0_radio_time = radio_time;
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|
|
|
assign radio1_radio_time = radio_time;
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|
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endmodule
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