Ryan Marlow
a90444c784
Module description: Clock divider. Generates an output clock that is 1/N times the frequency of the input clock. Original-commit: 71bdcd22f07162687771d374178ad0372783bd45
69 lines
1.4 KiB
Makefile
69 lines
1.4 KiB
Makefile
#
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# Copyright 2013 Ettus Research LLC
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# Copyright 2017 Ettus Research, a National Instruments Company
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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##################################################
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# Control Lib Sources
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##################################################
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CONTROL_LIB_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/control/, \
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ad5662_auto_spi.v \
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arb_qualify_master.v \
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axi_crossbar.v \
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axi_crossbar_regport.v \
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axi_fifo_header.v \
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axi_forwarding_cam.v \
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axi_setting_reg.v \
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axi_slave_mux.v \
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axi_test_vfifo.v \
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bin2gray.v \
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binary_encoder.v \
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clock_div.v \
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db_control.v \
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fe_control.v \
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filter_bad_sid.v \
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gearbox_2x1.v \
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gpio_atr_io.v \
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gpio_atr.v \
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gray2bin.v \
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por_gen.v \
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priority_encoder_one_hot.v \
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priority_encoder.v \
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ram_2port_impl.vh \
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ram_2port.v \
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reset_sync.v \
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s7_icap_wb.v \
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serial_to_settings.v \
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setting_reg.v \
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settings_bus_mux.v \
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settings_bus_timed_2clk.v \
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simple_i2c_core.v \
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simple_spi_core.v \
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simple_spi_core_64bit.v \
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synchronizer_impl.v \
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synchronizer.v \
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pulse_synchronizer.v \
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user_settings.v \
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axil_regport_master.v \
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axil_to_ni_regport.v \
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regport_resp_mux.v \
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regport_to_xbar_settingsbus.v \
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regport_to_settingsbus.v \
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pulse_stretch.v \
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pulse_stretch_min.v \
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mdio_master.v \
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map/cam_priority_encoder.v \
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map/cam_bram.v \
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map/cam_srl.v \
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map/cam.v \
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map/kv_map.v \
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map/axis_muxed_kv_map.v \
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axil_ctrlport_master.v\
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handshake.v\
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ctrlport_to_regport.v \
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glitch_free_mux.v \
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regport_if.sv \
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))
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