The main changes included are:
- Variant-dependent pin-out instantiation.
- Update clocking scheme in top level file
to include XO3 PLL
- Add ability to shift outgoing data for
the GPIO communication interface with
the X410 FPGA.
- Include project files required to build
the XO3 variant of the ZBX CPLD.
- Add build flow for Lattice Diamond designs.
- Add ability to build XO3 variant of ZBX CPLD.
Original-commit: 2c7813acb21383f302353a1b6cf57f0946fa0b6b
Javier Valenzuela
a6fc53b4e6