423 lines
14 KiB
Verilog
423 lines
14 KiB
Verilog
//
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// Copyright 2022 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: e320_sfp_wrapper
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//
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// Description:
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//
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// Wrapper for SFP port, including support for Aurora, 10 GbE, and 1 GbE.
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//
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// Parameters:
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//
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// PROTOCOL : Must be "10GbE", "1GbE", "Aurora", or "Disabled".
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// REG_DWIDTH : Data width of the AXI-Lite interface and RegPort
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// REG_AWIDTH : Address width of the AXI-Lite interface and RegPort
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// PORTNUM : Port number
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// MDIO_EN : Enables internal MDIO master
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// MDIO_PHYADDR : Address to use for the MDIO
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// BYTE_MTU : Log base 2 of the MTU in bytes
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// RFNOC_PROTOVER : RFNoC protocol version to be reported by transport
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// adapters.
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// NODE_INST : RFNoC transport adapter node instance for this port
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// EN_RX_KV_MAP_CFG : Enable KV-map configuration port on transport adapter
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// EN_RX_RAW_PYLD : Enable raw UDP support on transport adapter
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//
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`default_nettype none
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module e320_sfp_wrapper #(
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parameter PROTOCOL = "10GbE",
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parameter DWIDTH = 32,
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parameter AWIDTH = 14,
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parameter [7:0] PORTNUM = 8'd0,
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parameter MDIO_EN = 0,
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parameter [4:0] MDIO_PHYADDR = 5'd0,
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parameter BYTE_MTU = $clog2(8192),
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parameter [15:0] RFNOC_PROTOVER = {8'd1, 8'd0},
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parameter NODE_INST = 0,
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parameter EN_RX_KV_MAP_CFG = 1,
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parameter EN_RX_RAW_PYLD = 1
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) (
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// Resets
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input wire areset,
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input wire bus_rst,
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// Clocks
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input wire gt_refclk,
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input wire gb_refclk,
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input wire misc_clk,
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input wire bus_clk,
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// AXI-Lite
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input wire s_axi_aclk,
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input wire s_axi_aresetn,
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input wire [ AWIDTH-1:0] s_axi_awaddr,
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input wire s_axi_awvalid,
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output wire s_axi_awready,
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input wire [ DWIDTH-1:0] s_axi_wdata,
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input wire [DWIDTH/8-1:0] s_axi_wstrb,
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input wire s_axi_wvalid,
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output wire s_axi_wready,
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output wire [ 1:0] s_axi_bresp,
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output wire s_axi_bvalid,
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input wire s_axi_bready,
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input wire [ AWIDTH-1:0] s_axi_araddr,
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input wire s_axi_arvalid,
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output wire s_axi_arready,
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output wire [ DWIDTH-1:0] s_axi_rdata,
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output wire [ 1:0] s_axi_rresp,
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output wire s_axi_rvalid,
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input wire s_axi_rready,
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// SFP high-speed IO
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output wire txp,
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output wire txn,
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input wire rxp,
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input wire rxn,
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// SFP low-speed IO
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input wire sfpp_present_n,
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input wire sfpp_rxlos,
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input wire sfpp_tx_fault,
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output wire sfpp_tx_disable,
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// GT Common
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input wire qpllrefclklost,
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input wire qplllock,
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input wire qplloutclk,
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input wire qplloutrefclk,
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output wire qpllreset,
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// Aurora MMCM
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input wire mmcm_locked,
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output wire gt_pll_lock,
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output wire gt_tx_out_clk_unbuf,
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// Ethernet to RFNoC
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output wire [63:0] e2v_tdata,
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output wire e2v_tlast,
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output wire e2v_tvalid,
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input wire e2v_tready,
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// RFNoC to Ethernet
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input wire [63:0] v2e_tdata,
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input wire v2e_tlast,
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input wire v2e_tvalid,
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output wire v2e_tready,
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// Ethernet to CPU
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output wire [63:0] e2c_tdata,
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output wire [ 7:0] e2c_tkeep,
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output wire e2c_tlast,
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output wire e2c_tvalid,
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input wire e2c_tready,
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// CPU to Ethernet
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input wire [63:0] c2e_tdata,
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input wire [ 7:0] c2e_tkeep,
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input wire c2e_tlast,
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input wire c2e_tvalid,
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output wire c2e_tready,
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// Misc
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output wire [31:0] port_info,
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input wire [15:0] device_id,
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output wire link_up,
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output wire activity
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);
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localparam REG_BASE_SFP_IO = 14'h0;
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localparam REG_BASE_ETH_SWITCH = 14'h1000;
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// AXI4-Lite to RegPort (PS to PL Register Access)
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wire reg_wr_req;
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wire [AWIDTH-1:0] reg_wr_addr;
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wire [DWIDTH-1:0] reg_wr_data;
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wire reg_rd_req;
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wire [AWIDTH-1:0] reg_rd_addr;
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wire reg_rd_resp, reg_rd_resp_io, reg_rd_resp_eth_if;
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wire [DWIDTH-1:0] reg_rd_data, reg_rd_data_io, reg_rd_data_eth_if;
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axil_regport_master #(
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.DWIDTH (DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64)
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.AWIDTH (AWIDTH), // Width of the address bus
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.WRBASE (0), // Write address base
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.RDBASE (0), // Read address base
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.TIMEOUT (10) // log2(timeout). Read will timeout after (2^TIMEOUT - 1) cycles
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) sfp_reg_mst_i (
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// Clock and reset
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.s_axi_aclk (s_axi_aclk),
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.s_axi_aresetn (s_axi_aresetn),
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// AXI4-Lite: Write address port (domain: s_axi_aclk)
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.s_axi_awaddr (s_axi_awaddr),
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.s_axi_awvalid (s_axi_awvalid),
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.s_axi_awready (s_axi_awready),
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// AXI4-Lite: Write data port (domain: s_axi_aclk)
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.s_axi_wdata (s_axi_wdata),
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.s_axi_wstrb (s_axi_wstrb),
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.s_axi_wvalid (s_axi_wvalid),
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.s_axi_wready (s_axi_wready),
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// AXI4-Lite: Write response port (domain: s_axi_aclk)
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.s_axi_bresp (s_axi_bresp),
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.s_axi_bvalid (s_axi_bvalid),
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.s_axi_bready (s_axi_bready),
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// AXI4-Lite: Read address port (domain: s_axi_aclk)
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.s_axi_araddr (s_axi_araddr),
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.s_axi_arvalid (s_axi_arvalid),
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.s_axi_arready (s_axi_arready),
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// AXI4-Lite: Read data port (domain: s_axi_aclk)
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.s_axi_rdata (s_axi_rdata),
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.s_axi_rresp (s_axi_rresp),
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.s_axi_rvalid (s_axi_rvalid),
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.s_axi_rready (s_axi_rready),
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// Register port: Write port (domain: reg_clk)
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.reg_clk (bus_clk),
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.reg_wr_req (reg_wr_req),
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.reg_wr_addr (reg_wr_addr),
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.reg_wr_data (reg_wr_data),
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// Register port: Read port (domain: reg_clk)
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.reg_rd_req (reg_rd_req),
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.reg_rd_addr (reg_rd_addr),
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.reg_rd_resp (reg_rd_resp),
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.reg_rd_data (reg_rd_data)
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);
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// RegPort Mux for response
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regport_resp_mux #(
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.WIDTH (DWIDTH),
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.NUM_SLAVES (2)
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) reg_resp_mux_i (
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.clk(bus_clk), .reset(bus_rst),
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.sla_rd_resp({reg_rd_resp_eth_if, reg_rd_resp_io}),
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.sla_rd_data({reg_rd_data_eth_if, reg_rd_data_io}),
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.mst_rd_resp(reg_rd_resp), .mst_rd_data(reg_rd_data)
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);
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wire [63:0] sfpo_tdata, sfpi_tdata;
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wire [3:0] sfpo_tuser, sfpi_tuser;
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wire sfpo_tlast, sfpi_tlast, sfpo_tvalid, sfpi_tvalid, sfpo_tready, sfpi_tready;
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e320_mgt_io_core #(
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.PROTOCOL (PROTOCOL),
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.REG_BASE (REG_BASE_SFP_IO),
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.REG_DWIDTH (DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64)
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.REG_AWIDTH (AWIDTH), // Width of the address bus
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.MDIO_EN (MDIO_EN),
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.MDIO_PHYADDR (MDIO_PHYADDR),
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.PORTNUM (PORTNUM)
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) mgt_io_i (
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.areset (areset),
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.gt_refclk (gt_refclk),
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.gb_refclk (gb_refclk),
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.misc_clk (misc_clk),
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.bus_rst (bus_rst),
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.bus_clk (bus_clk),
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.txp (txp),
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.txn (txn),
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.rxp (rxp),
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.rxn (rxn),
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.sfpp_rxlos (sfpp_rxlos),
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.sfpp_tx_fault (sfpp_tx_fault),
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.sfpp_tx_disable(sfpp_tx_disable),
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// RegPort
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.reg_wr_req (reg_wr_req),
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.reg_wr_addr (reg_wr_addr),
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.reg_wr_data (reg_wr_data),
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.reg_rd_req (reg_rd_req),
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.reg_rd_addr (reg_rd_addr),
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.reg_rd_resp (reg_rd_resp_io),
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.reg_rd_data (reg_rd_data_io),
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// RFNoC to Ethernet
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.s_axis_tdata (sfpi_tdata),
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.s_axis_tuser (sfpi_tuser),
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.s_axis_tlast (sfpi_tlast),
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.s_axis_tvalid (sfpi_tvalid),
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.s_axis_tready (sfpi_tready),
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// Ethernet to RFNoC
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.m_axis_tdata (sfpo_tdata),
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.m_axis_tuser (sfpo_tuser),
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.m_axis_tlast (sfpo_tlast),
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.m_axis_tvalid (sfpo_tvalid),
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.m_axis_tready (sfpo_tready),
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.port_info (port_info),
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.link_up (link_up),
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.activity (activity)
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);
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generate
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// Tie off the Ethernet switch for these protocols that do not use it.
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if (PROTOCOL == "Aurora" || PROTOCOL == "Disabled") begin : gen_no_eth
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//set unused wires to default value
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assign e2c_tdata = 64'h0;
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assign e2c_tkeep = 8'h0;
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assign e2c_tlast = 1'b0;
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assign e2c_tvalid = 1'b0;
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assign c2e_tready = 1'b1;
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assign reg_rd_resp_eth_if = 1'b0;
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assign reg_rd_data_eth_if = 'h0;
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end else begin : gen_eth
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wire [3:0] e2c_tuser;
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wire [3:0] c2e_tuser;
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// In AXI Stream, tkeep is the byte qualifier that indicates
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// whether the content of the associated byte
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// of TDATA is processed as part of the data stream.
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// tuser as used in eth_interface is the number of valid bytes
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// Converting tuser to tkeep for ingress packets
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assign e2c_tkeep = ~e2c_tlast ? 8'b1111_1111
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: (e2c_tuser[2:0] == 3'd0) ? 8'b1111_1111
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: (e2c_tuser[2:0] == 3'd1) ? 8'b0000_0001
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: (e2c_tuser[2:0] == 3'd2) ? 8'b0000_0011
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: (e2c_tuser[2:0] == 3'd3) ? 8'b0000_0111
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: (e2c_tuser[2:0] == 3'd4) ? 8'b0000_1111
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: (e2c_tuser[2:0] == 3'd5) ? 8'b0001_1111
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: (e2c_tuser[2:0] == 3'd6) ? 8'b0011_1111
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: 8'b0111_1111;
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// Converting tkeep to tuser for egress packets
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assign c2e_tuser = ~c2e_tlast ? 4'd0
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: (c2e_tkeep == 8'b1111_1111) ? 4'd0
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: (c2e_tkeep == 8'b0111_1111) ? 4'd7
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: (c2e_tkeep == 8'b0011_1111) ? 4'd6
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: (c2e_tkeep == 8'b0001_1111) ? 4'd5
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: (c2e_tkeep == 8'b0000_1111) ? 4'd4
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: (c2e_tkeep == 8'b0000_0111) ? 4'd3
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: (c2e_tkeep == 8'b0000_0011) ? 4'd2
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: (c2e_tkeep == 8'b0000_0001) ? 4'd1
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: 4'd0;
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if (EN_RX_KV_MAP_CFG || EN_RX_RAW_PYLD) begin : gen_eth_ipv4_interface_wrapper
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eth_ipv4_interface_wrapper #(
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.PROTOVER (RFNOC_PROTOVER),
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.CPU_FIFO_SIZE (BYTE_MTU),
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.CHDR_FIFO_SIZE (BYTE_MTU),
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.NODE_INST (NODE_INST),
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.REG_AWIDTH (AWIDTH),
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.BASE (REG_BASE_ETH_SWITCH),
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.SYNC (1),
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.EN_RX_KV_MAP_CFG (EN_RX_KV_MAP_CFG),
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.EN_RX_RAW_PYLD (EN_RX_RAW_PYLD)
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) eth_ipv4_interface_wrapper_i (
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.bus_clk (bus_clk),
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.bus_rst (bus_rst),
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.device_id (device_id),
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.reg_wr_req (reg_wr_req),
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.reg_wr_addr (reg_wr_addr),
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.reg_wr_data (reg_wr_data),
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.reg_rd_req (reg_rd_req),
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.reg_rd_addr (reg_rd_addr),
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.reg_rd_resp (reg_rd_resp_eth_if),
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.reg_rd_data (reg_rd_data_eth_if),
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.my_mac (),
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.my_ip (),
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.my_udp_chdr_port (),
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.eth_clk (bus_clk),
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.eth_rst (bus_rst),
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.eth_pause_req (),
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.eth_tx_tdata (sfpi_tdata),
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.eth_tx_tuser (sfpi_tuser),
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.eth_tx_tkeep (),
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.eth_tx_tlast (sfpi_tlast),
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.eth_tx_tvalid (sfpi_tvalid),
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.eth_tx_tready (sfpi_tready),
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.eth_rx_tdata (sfpo_tdata),
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.eth_rx_tuser (sfpo_tuser),
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.eth_rx_tlast (sfpo_tlast),
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.eth_rx_tvalid (sfpo_tvalid),
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.eth_rx_tready (sfpo_tready),
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.e2v_tdata (e2v_tdata),
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.e2v_tlast (e2v_tlast),
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.e2v_tvalid (e2v_tvalid),
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.e2v_tready (e2v_tready),
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.v2e_tdata (v2e_tdata),
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.v2e_tlast (v2e_tlast),
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.v2e_tvalid (v2e_tvalid),
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.v2e_tready (v2e_tready),
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.cpu_clk (bus_clk),
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.cpu_rst (bus_rst),
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.e2c_tdata (e2c_tdata),
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.e2c_tuser (e2c_tuser),
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.e2c_tlast (e2c_tlast),
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.e2c_tvalid (e2c_tvalid),
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.e2c_tready (e2c_tready),
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.c2e_tdata (c2e_tdata),
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.c2e_tuser (c2e_tuser),
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.c2e_tlast (c2e_tlast),
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.c2e_tvalid (c2e_tvalid),
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.c2e_tready (c2e_tready)
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);
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end // gen_eth_ipv4_interface_wrapper
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else begin : gen_eth_interface
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eth_interface #(
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.PROTOVER (RFNOC_PROTOVER),
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.MTU (BYTE_MTU-3), // Log base 2 of the MTU in 64-words
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.NODE_INST (NODE_INST),
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.REG_AWIDTH (AWIDTH),
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.BASE (REG_BASE_ETH_SWITCH)
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) eth_interface (
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.clk (bus_clk),
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.reset (bus_rst),
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.device_id (device_id),
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.reg_wr_req (reg_wr_req),
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.reg_wr_addr (reg_wr_addr),
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.reg_wr_data (reg_wr_data),
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.reg_rd_req (reg_rd_req),
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.reg_rd_addr (reg_rd_addr),
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.reg_rd_resp (reg_rd_resp_eth_if),
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.reg_rd_data (reg_rd_data_eth_if),
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.my_mac (),
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.my_ip (),
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.my_udp_port (),
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.eth_tx_tdata (sfpi_tdata),
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.eth_tx_tuser (sfpi_tuser),
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.eth_tx_tlast (sfpi_tlast),
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.eth_tx_tvalid (sfpi_tvalid),
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.eth_tx_tready (sfpi_tready),
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.eth_rx_tdata (sfpo_tdata),
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.eth_rx_tuser (sfpo_tuser),
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.eth_rx_tlast (sfpo_tlast),
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.eth_rx_tvalid (sfpo_tvalid),
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.eth_rx_tready (sfpo_tready),
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.e2v_tdata (e2v_tdata),
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.e2v_tlast (e2v_tlast),
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.e2v_tvalid (e2v_tvalid),
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.e2v_tready (e2v_tready),
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.v2e_tdata (v2e_tdata),
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.v2e_tlast (v2e_tlast),
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.v2e_tvalid (v2e_tvalid),
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.v2e_tready (v2e_tready),
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.e2c_tdata (e2c_tdata),
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.e2c_tuser (e2c_tuser),
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.e2c_tlast (e2c_tlast),
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.e2c_tvalid (e2c_tvalid),
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.e2c_tready (e2c_tready),
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.c2e_tdata (c2e_tdata),
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.c2e_tuser (c2e_tuser),
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.c2e_tlast (c2e_tlast),
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.c2e_tvalid (c2e_tvalid),
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.c2e_tready (c2e_tready)
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);
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end // gen_eth_interface
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end // gen_eth
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endgenerate
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endmodule // e320_sfp_wrapper
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`default_nettype wire
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