Wade Fife
c322899053
This adds DRAM support to E31x devices. Due to the size of the DDR3 memory controller, it is not enabled by default. You can include the memory controller IP in the build by adding the DRAM environment variable to your build. For example: DRAM=1 make E310_SG3 Original-commit: 788fef11ef890c6dcee3be495fc381bcf2990d3b
22 lines
608 B
Systemverilog
22 lines
608 B
Systemverilog
//
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// Copyright 2022 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Header: rfnoc_image_core.vh (for e31x)
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//
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// Description:
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//
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// This is the header file for the RFNoC Image Core.
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//
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// This file was automatically generated by the RFNoC image builder tool.
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// Re-running that tool will overwrite this file!
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//
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// File generated on: 2022-02-07T19:18:28.012652
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// Source: e310_rfnoc_image_core.yml
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// Source SHA256: 7fef622f1ae280dd7573abd823c7a6bbecf51921a74cea948e6bfb9f8f65e2cc
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//
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`define CHDR_WIDTH 64
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`define RFNOC_PROTOVER { 8'd1, 8'd0 }
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