Wade Fife
31c638f98c
This fixes some issues with the 2021.1 version of the 10 GbE IP. In the new version, link status is sporadically detected by the Xilinx IP when nothing is connected to the port. Also, when the SFP is inserted, the link status goes up and down multiple times. This change fixes this by adding a counter and only considering it "linked" when the link has been stable for some amount of time. Original-commit: 846c7be2e42f1db6d7c7cc0b1128e014f83e3bae
324 lines
11 KiB
Verilog
324 lines
11 KiB
Verilog
//
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// Copyright 2021 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: ten_gige_phy
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//
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// Description:
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//
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// Wrapper for the Xilinx xxv_ethernet IP (10G/25G Ethernet Subsystem).
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//
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module ten_gige_phy (
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input wire areset,
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input wire dclk,
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output wire xgmii_clk,
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// Transceiver IO
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output wire txp,
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output wire txn,
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input wire rxp,
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input wire rxn,
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// XGMII Interface
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input wire [63:0] xgmii_txd,
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input wire [ 7:0] xgmii_txc,
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output wire [63:0] xgmii_rxd,
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output wire [ 7:0] xgmii_rxc,
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// GTYE4_COMMON
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input wire qpll0_refclk,
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input wire qpll0_clk,
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input wire qpll0_lock,
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output wire qpll0_reset,
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input wire qpll1_refclk,
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input wire qpll1_clk,
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input wire qpll1_lock,
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output wire qpll1_reset,
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output wire rxrecclkout,
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output wire [7:0] core_status,
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output reg reset_done
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);
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// Create a constant that tells us if we're in simulation or synthesis.
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localparam SIMULATION = 0
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//synthesis translate_off
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+ 1
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//synthesis translate_on
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;
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// xgmii_clk frequency in Hz
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localparam XGMII_FREQ = 125_000_000;
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// Cycles to wait before period reset while link is down.
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localparam RESET_WAIT = XGMII_FREQ/2;
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// Cycles to wait before reporting the link is up. Use a much smaller number
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// in simulation to save time.
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localparam LINK_WAIT = SIMULATION ? (125) : RESET_WAIT;
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// Duration of reset in cycles (must be less than LINK_WAIT)
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localparam LINK_RST_DURATION = 100;
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// Width of the wait counter. Must be wide enough for the WAIT values above.
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localparam WAIT_W = $clog2(RESET_WAIT+1);
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wire rx_serdes_reset;
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wire tx_reset;
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wire rx_reset;
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wire a_gt_reset_tx_done, gt_reset_tx_done;
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wire a_gt_reset_rx_done, gt_reset_rx_done;
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wire stat_rx_status_tmp;
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reg stat_rx_status = 0;
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reg [WAIT_W-1:0] wait_count = 0;
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reg gt_rx_reset_in = 0;
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//---------------------------------------------------------------------------
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// Xilinx 10G/25G IP High Speed Ethernet Subsystem Instance
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//---------------------------------------------------------------------------
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// All connections below follow the Xilinx IP example design, except that
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// rx_core_clk is driven by tx_mii_clk instead of rx_clk_out. This puts the
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// RX and TX interfaces on the same clock domain.
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// gtwiz_reset_qpll1reset_out is not connected to qpll1reset in the example
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// design. Instead, qpll1reset is connected to 0.
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assign qpll1_reset = 1'b0;
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xge_pcs_pma xge_pcs_pma_i (
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.gt_rxp_in_0 (rxp),
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.gt_rxn_in_0 (rxn),
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.gt_txp_out_0 (txp),
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.gt_txn_out_0 (txn),
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.tx_mii_clk_0 (xgmii_clk),
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.rx_core_clk_0 (xgmii_clk),
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.rx_clk_out_0 (),
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.gt_loopback_in_0 (3'b0),
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.rx_reset_0 (rx_reset),
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.rxrecclkout_0 (rxrecclkout),
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.rx_mii_d_0 (xgmii_rxd),
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.rx_mii_c_0 (xgmii_rxc),
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.ctl_rx_test_pattern_0 (1'b0),
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.ctl_rx_test_pattern_enable_0 (1'b0),
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.ctl_rx_data_pattern_select_0 (1'b0),
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.ctl_rx_prbs31_test_pattern_enable_0 (1'b0),
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.stat_rx_block_lock_0 (),
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.stat_rx_framing_err_valid_0 (),
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.stat_rx_framing_err_0 (),
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.stat_rx_hi_ber_0 (),
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.stat_rx_valid_ctrl_code_0 (),
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.stat_rx_bad_code_0 (),
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.stat_rx_bad_code_valid_0 (),
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.stat_rx_error_valid_0 (),
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.stat_rx_error_0 (),
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.stat_rx_fifo_error_0 (),
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.stat_rx_local_fault_0 (),
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.stat_rx_status_0 (stat_rx_status_tmp), // rx_core_clk_0 domain
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.tx_reset_0 (tx_reset),
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.tx_mii_d_0 (xgmii_txd),
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.tx_mii_c_0 (xgmii_txc),
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.ctl_tx_test_pattern_0 (1'b0),
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.ctl_tx_test_pattern_enable_0 (1'b0),
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.ctl_tx_test_pattern_select_0 (1'b0),
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.ctl_tx_data_pattern_select_0 (1'b0),
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.ctl_tx_test_pattern_seed_a_0 (58'b0),
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.ctl_tx_test_pattern_seed_b_0 (58'b0),
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.ctl_tx_prbs31_test_pattern_enable_0 (1'b0),
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.stat_tx_local_fault_0 (),
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.gt_dmonitorout_0 (),
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.gt_eyescandataerror_0 (),
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.gt_eyescanreset_0 (1'b0),
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.gt_eyescantrigger_0 (1'b0),
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.gt_pcsrsvdin_0 (16'b0),
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.gt_rxbufreset_0 (1'b0),
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.gt_rxbufstatus_0 (),
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.gt_rxcdrhold_0 (1'b0),
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.gt_rxcommadeten_0 (1'b0),
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.gt_rxdfeagchold_0 (1'b0),
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.gt_rxdfelpmreset_0 (1'b0),
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.gt_rxlatclk_0 (1'b0),
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.gt_rxlpmen_0 (1'b0),
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.gt_rxpcsreset_0 (1'b0),
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.gt_rxpmareset_0 (1'b0),
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.gt_rxpolarity_0 (1'b0),
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.gt_rxprbscntreset_0 (1'b0),
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.gt_rxprbserr_0 (),
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.gt_rxprbssel_0 (4'b0),
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.gt_rxrate_0 (3'b0),
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.gt_rxslide_in_0 (1'b0),
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.gt_rxstartofseq_0 (),
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.gt_txbufstatus_0 (),
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.gt_txinhibit_0 (1'b0),
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.gt_txlatclk_0 (1'b0),
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.gt_txmaincursor_0 (7'h50),
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.gt_txpcsreset_0 (1'b0),
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.gt_txpmareset_0 (1'b0),
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.gt_txpolarity_0 (1'b0),
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.gt_txpostcursor_0 (5'b0),
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.gt_txprbsforceerr_0 (1'b0),
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.gt_txelecidle_0 (1'b0),
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.gt_txprbssel_0 (4'b0),
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.gt_txprecursor_0 (5'b0),
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.gt_txdiffctrl_0 (5'h18),
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.gt_drpdo_0 (),
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.gt_drprdy_0 (),
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.gt_drpen_0 (1'b0),
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.gt_drpwe_0 (1'b0),
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.gt_drpaddr_0 (10'b0),
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.gt_drpdi_0 (16'b0),
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.gt_drpclk_0 (dclk),
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.gt_drprst_0 (1'b0),
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.gtpowergood_out_0 (),
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.txoutclksel_in_0 (3'b101),
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.rxoutclksel_in_0 (3'b101),
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.rx_serdes_reset_0 (rx_serdes_reset),
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.gt_reset_all_in_0 (areset),
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.gt_tx_reset_in_0 (1'b0),
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.gt_rx_reset_in_0 (gt_rx_reset_in),
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.gt_reset_tx_done_out_0 (a_gt_reset_tx_done),
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.gt_reset_rx_done_out_0 (a_gt_reset_rx_done),
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.sys_reset (areset),
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.dclk (dclk),
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.qpll0clk_in (qpll0_clk),
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.qpll0refclk_in (qpll0_refclk),
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.qpll1clk_in (qpll1_clk),
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.qpll1refclk_in (qpll1_refclk),
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.gtwiz_reset_qpll0lock_in (qpll0_lock),
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.gtwiz_reset_qpll1lock_in (qpll1_lock),
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.gtwiz_reset_qpll0reset_out (qpll0_reset),
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.gtwiz_reset_qpll1reset_out ()
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);
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//---------------------------------------------------------------------------
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// Status
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//---------------------------------------------------------------------------
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assign core_status[7:1] = 0; // Unused
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assign core_status[0] = stat_rx_status; // Link status
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// Safely combine the RX and TX reset done signals into a single glitch-free
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// signal.
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synchronizer sync_reset_tx_done (
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.clk (xgmii_clk),
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.rst (1'b0),
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.in (a_gt_reset_tx_done),
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.out (gt_reset_tx_done)
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);
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synchronizer sync_reset_rx_done (
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.clk (xgmii_clk),
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.rst (1'b0),
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.in (a_gt_reset_rx_done),
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.out (gt_reset_rx_done)
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);
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always @(posedge xgmii_clk) begin : ResetDoneProc
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reset_done <= gt_reset_tx_done & gt_reset_rx_done;
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end
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//---------------------------------------------------------------------------
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// Reset Logic
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//---------------------------------------------------------------------------
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// The reset synchronization below is taken from the example design, except
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// that rx_clk_out was replaced by tx_mii_clk (xgmii_clk).
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synchronizer sync_rx_serdes_reset (
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.clk (xgmii_clk),
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.rst (1'b0),
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.in (~a_gt_reset_rx_done),
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.out (rx_serdes_reset)
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);
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synchronizer sync_tx_reset (
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.clk (xgmii_clk),
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.rst (1'b0),
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.in (~a_gt_reset_tx_done),
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.out (tx_reset)
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);
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synchronizer sync_rx_reset (
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.clk (xgmii_clk),
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.rst (1'b0),
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.in (~a_gt_reset_rx_done),
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.out (rx_reset)
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);
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localparam [1:0] ST_IDLE = 0;
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localparam [1:0] ST_RESET = 1;
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localparam [1:0] ST_WAIT_FOR_LINK = 2;
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localparam [1:0] ST_LINKED = 3;
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reg [1:0] state = ST_IDLE;
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// This state machine resets the RX GT part of the Xilinx IP periodically
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// while the link is down. Once the Xilinx IP reports the link as up, it
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// waits a bit to make sure the link is stable before reporting that it is
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// up. This allows us to tolerate a some amount of flakiness while the port
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// is being plugged in.
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always @(posedge xgmii_clk, posedge areset) begin
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if (areset) begin
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gt_rx_reset_in <= 0;
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wait_count <= 0;
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stat_rx_status <= 0;
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state <= ST_IDLE;
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end else begin
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case (state)
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ST_IDLE : begin
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// Wait for a delay then reset the RX GT core if the link is down.
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wait_count <= wait_count + 1;
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if (stat_rx_status_tmp) begin
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// Link indication asserted, so let's see if it's stable.
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wait_count <= 0;
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state <= ST_WAIT_FOR_LINK;
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end else if (wait_count >= RESET_WAIT) begin
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// Link didn't assert during our wait, so reset the core, in case
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// it's in a bad state.
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wait_count <= 0;
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state <= ST_RESET;
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end
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end
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ST_RESET : begin
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// Reset the RX GT logic
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gt_rx_reset_in <= 1;
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wait_count <= wait_count + 1;
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if (wait_count >= LINK_RST_DURATION) begin
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// Reset is done, so deassert and then try again
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gt_rx_reset_in <= 0;
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wait_count <= 0;
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state <= ST_IDLE;
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end
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end
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ST_WAIT_FOR_LINK : begin
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// Wait for a while to make sure the link is stable
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wait_count <= wait_count + 1;
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if (!stat_rx_status_tmp) begin
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// Link was not stable!
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wait_count <= 0;
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state <= ST_RESET;
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end else if (wait_count >= LINK_WAIT) begin
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// Link stayed stable during the wait
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wait_count <= 0;
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state <= ST_LINKED;
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end
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end
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ST_LINKED : begin
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// We've had a solid link for a while know, so let's call it good.
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wait_count <= 0;
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stat_rx_status <= 1;
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if (!stat_rx_status_tmp) begin
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stat_rx_status <= 0;
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state <= ST_RESET;
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end
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end
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endcase
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end
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end
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endmodule
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