157 lines
4.1 KiB
Systemverilog
157 lines
4.1 KiB
Systemverilog
//
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// Copyright 2011 Ettus Research LLC
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// Copyright 2018 Ettus Research, a National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Used by ram_2port.v
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// Requires `RAM_MOD_NAME and `RAM_DIRECTIVE to be defined
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module `RAM_MOD_NAME #(
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parameter DWIDTH = 32, // Width of the memory block
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parameter AWIDTH = 9, // log2 of the depth of the memory block
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parameter RW_MODE = "READ-FIRST", // Read-write mode {READ-FIRST, WRITE-FIRST, NO-CHANGE, B-READ-ONLY}
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parameter OUT_REG = 0, // Instantiate an output register? (+1 cycle of read latency)
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parameter INIT_FILE = "" // Optionally initialize memory with this file
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) (
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input wire clka,
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input wire ena,
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input wire wea,
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input wire [AWIDTH-1:0] addra,
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input wire [DWIDTH-1:0] dia,
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output wire [DWIDTH-1:0] doa,
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input wire clkb,
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input wire enb,
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input wire web,
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input wire [AWIDTH-1:0] addrb,
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input wire [DWIDTH-1:0] dib,
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output wire [DWIDTH-1:0] dob
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);
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`RAM_DIRECTIVE reg [DWIDTH-1:0] ram [(1<<AWIDTH)-1:0];
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// Initialize ram to a specified file or to all zeros to match hardware
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generate if (INIT_FILE != "") begin
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initial begin
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$readmemh(INIT_FILE, ram, 0, (1<<AWIDTH)-1);
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end
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end else begin
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integer i;
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initial begin
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for (i = 0; i < (1<<AWIDTH); i = i + 1) begin
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ram[i] = {DWIDTH{1'b0}};
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end
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end
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end endgenerate
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reg [DWIDTH-1:0] doa_r = 'h0, dob_r = 'h0;
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generate if (OUT_REG == 1) begin
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// A 2 clock cycle read latency with improve clock-to-out timing
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reg [DWIDTH-1:0] doa_rr = 'h0, dob_rr = 'h0;
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always @(posedge clka)
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if (ena) begin
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doa_rr <= doa_r;
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end
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always @(posedge clkb)
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if (enb) begin
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dob_rr <= dob_r;
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end
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assign doa = doa_rr;
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assign dob = dob_rr;
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end else begin
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// A 1 clock cycle read latency at the cost of a longer clock-to-out timing
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assign doa = doa_r;
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assign dob = dob_r;
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end endgenerate
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generate if (RW_MODE == "READ-FIRST") begin
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// When data is written, the prior memory contents at the write
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// address are presented on the output port.
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always @(posedge clka) begin
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if (ena) begin
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if (wea) begin
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ram[addra] <= dia;
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end
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doa_r <= ram[addra];
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end
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end
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always @(posedge clkb) begin
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if (enb) begin
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if (web) begin
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ram[addrb] <= dib;
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end
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dob_r <= ram[addrb];
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end
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end
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end else if (RW_MODE == "WRITE-FIRST") begin
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// The data being written to the RAM also resides on the output port.
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always @(posedge clka) begin
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if (ena) begin
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if (wea) begin
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ram[addra] <= dia;
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doa_r <= dia;
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end else begin
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doa_r <= ram[addra];
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end
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end
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end
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always @(posedge clkb) begin
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if (enb) begin
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if (web) begin
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ram[addrb] <= dib;
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dob_r <= dib;
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end else begin
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dob_r <= ram[addrb];
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end
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end
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end
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end else if (RW_MODE == "NO-CHANGE") begin
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// This is a no change RAM which retains the last read value on the output during writes
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// which is the most power efficient mode.
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always @(posedge clka) begin
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if (ena) begin
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if (wea) begin
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ram[addra] <= dia;
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end else begin
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doa_r <= ram[addra];
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end
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end
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end
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always @(posedge clkb) begin
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if (enb) begin
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if (web) begin
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ram[addrb] <= dib;
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end else begin
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dob_r <= ram[addrb];
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end
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end
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end
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end else if (RW_MODE == "B-READ-ONLY") begin
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// This is a RAM where port A is using READ-FIRST strategy and port B supports read only.
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always @(posedge clka) begin
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if (ena) begin
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if (wea) begin
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ram[addra] <= dia;
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end
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doa_r <= ram[addra];
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end
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end
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always @(posedge clkb) begin
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if (enb) begin
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dob_r <= ram[addrb];
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end
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end
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end else begin
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ERROR_Invalid_RW_MODE_selection();
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end endgenerate
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endmodule
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