215 lines
7.3 KiB
Verilog
215 lines
7.3 KiB
Verilog
//
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// Copyright 2021 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: rfdc_timing_control
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//
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// Description:
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//
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// This module handles timed register writes for the RFDC, such as NCO reset
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// control. Timed commands are handled by the ctrlport_timer module.
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//
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// Parameters:
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//
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// NUM_DBOARDS : Number of daughter boards to support
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//
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`default_nettype none
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module rfdc_timing_control #(
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parameter NUM_DBOARDS = 2
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) (
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// Clocks and resets
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input wire [ 1*NUM_DBOARDS-1:0] clk,
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input wire [ 1*NUM_DBOARDS-1:0] rst,
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// CtrlPort Slave (from RFNoC Radio Block)
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input wire [ 1*NUM_DBOARDS-1:0] s_ctrlport_req_wr,
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input wire [ 1*NUM_DBOARDS-1:0] s_ctrlport_req_rd,
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input wire [ 20*NUM_DBOARDS-1:0] s_ctrlport_req_addr,
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input wire [ 32*NUM_DBOARDS-1:0] s_ctrlport_req_data,
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output wire [ 1*NUM_DBOARDS-1:0] s_ctrlport_resp_ack,
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output wire [ 2*NUM_DBOARDS-1:0] s_ctrlport_resp_status,
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output wire [ 32*NUM_DBOARDS-1:0] s_ctrlport_resp_data,
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// RF Reset Control
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output reg start_nco_reset,
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input wire nco_reset_done,
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output reg [ 1*NUM_DBOARDS-1:0] adc_reset_pulse,
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output reg [ 1*NUM_DBOARDS-1:0] dac_reset_pulse
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);
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`include "regmap/rfdc_timing_regmap_utils.vh"
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// Reset registers
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reg [NUM_DBOARDS-1:0] reg_nco_reset_start = 0;
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genvar db;
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generate
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for (db = 0; db < NUM_DBOARDS; db = db+1) begin : gen_db_ctrlport
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//-----------------------------------------------------------------------
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// CtrlPort Breakdown
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//-----------------------------------------------------------------------
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wire nco_ctrlport_req_wr;
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wire nco_ctrlport_req_rd;
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wire [ 19:0] nco_ctrlport_req_addr;
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wire [ 31:0] nco_ctrlport_req_data;
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reg nco_ctrlport_resp_ack;
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reg [ 31:0] nco_ctrlport_resp_data;
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wire [ 1:0] nco_ctrlport_resp_status = 2'b0;
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wire nco_reset_done_clk;
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// When asserted, nco_reset_done will stay high until the next start_nco_reset
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// pulse, which by software design will not happen until this synchronizer
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// propagates and the converted nco_reset_done_clk is read.
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synchronizer #(
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.STAGES (2),
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.WIDTH (1),
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.INITIAL_VAL (1'h0)
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) synchronizer_nco_reset_done (
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.clk (clk[db]),
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.rst (rst[db]),
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.in (nco_reset_done),
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.out (nco_reset_done_clk)
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);
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assign nco_ctrlport_req_wr = s_ctrlport_req_wr [ 1*db+: 1];
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assign nco_ctrlport_req_rd = s_ctrlport_req_rd [ 1*db+: 1];
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assign nco_ctrlport_req_addr = s_ctrlport_req_addr [20*db+:20];
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assign nco_ctrlport_req_data = s_ctrlport_req_data [32*db+:32];
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assign s_ctrlport_resp_ack [ 1*db+: 1] = nco_ctrlport_resp_ack;
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assign s_ctrlport_resp_status [ 2*db+: 2] = nco_ctrlport_resp_data;
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assign s_ctrlport_resp_data [32*db+:32] = nco_ctrlport_resp_status;
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//-----------------------------------------------------------------------
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// RF Reset Control
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//-----------------------------------------------------------------------
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always @(posedge clk[db]) begin
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if (rst[db]) begin
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nco_ctrlport_resp_ack <= 0;
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reg_nco_reset_start[db] <= 0;
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nco_ctrlport_resp_data <= 'bX;
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end else begin
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// Default assignments
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reg_nco_reset_start[db] <= 0;
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adc_reset_pulse[db] <= 0;
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dac_reset_pulse[db] <= 0;
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nco_ctrlport_resp_ack <= 0;
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nco_ctrlport_resp_data <= 0;
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// Handle register reads
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if (nco_ctrlport_req_rd) begin
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case (nco_ctrlport_req_addr)
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NCO_RESET_REG: begin
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nco_ctrlport_resp_ack <= 1;
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nco_ctrlport_resp_data[NCO_RESET_DONE] <= nco_reset_done_clk;
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end
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GEARBOX_RESET_REG: begin
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nco_ctrlport_resp_ack <= 1;
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end
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endcase
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end
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// Handle register writes
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if (nco_ctrlport_req_wr) begin
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case (nco_ctrlport_req_addr)
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NCO_RESET_REG: begin
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nco_ctrlport_resp_ack <= 1;
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reg_nco_reset_start[db] <= nco_ctrlport_req_data[NCO_RESET_START];
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end
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GEARBOX_RESET_REG: begin
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nco_ctrlport_resp_ack <= 1;
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adc_reset_pulse[db] <= nco_ctrlport_req_data[ADC_RESET];
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dac_reset_pulse[db] <= nco_ctrlport_req_data[DAC_RESET];
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end
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endcase
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end
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end
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end
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end
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endgenerate
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//---------------------------------------------------------------------------
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// Merge NCO Start
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//---------------------------------------------------------------------------
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//
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// There are multiple DBs but only one NCO start pulse, which is expected to
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// happen on the clk[0] domain. This pulse will be used to align NCO updates
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// to the next SYSREF pulse, which is related to all clk[db] domains.
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//
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//---------------------------------------------------------------------------
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wire [NUM_DBOARDS-1:0] reg_nco_reset_start_clk0 = 0;
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genvar db_i;
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generate
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for (db_i = 0; db_i < NUM_DBOARDS; db_i = db_i+1) begin : gen_nco_start_sync
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pulse_synchronizer #(
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.MODE("PULSE"), .STAGES(2)
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) pulse_sync_nco_start (
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.clk_a(clk[db_i]), .rst_a(rst[db_i]), .pulse_a(reg_nco_reset_start[db_i]), .busy_a(),
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.clk_b(clk[0]), .pulse_b(reg_nco_reset_start_clk0[db_i])
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);
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end
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endgenerate
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always @(posedge clk[0]) begin
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if (rst[0]) begin
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start_nco_reset <= 0;
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end else begin
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start_nco_reset <= |reg_nco_reset_start_clk0;
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end
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end
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endmodule
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`default_nettype wire
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//XmlParse xml_on
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//
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//<regmap name="RFDC_TIMING_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
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// <group name="RFDC_TIMING_REGS">
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// <register name="NCO_RESET_REG" offset="0x00" size="32" readable="true" writable="true">
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// <info>NCO reset control register.</info>
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// <bitfield name="NCO_RESET_START" range="0" readable="false" strobe="true">
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// <info>Write a 1 to this bit to start a reset the RFDC's NCO.</info>
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// </bitfield>
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// <bitfield name="NCO_RESET_DONE" range="1" writable="false">
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// <info>When 1, indicates that the NCO reset has completed.</info>
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// </bitfield>
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// </register>
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// <register name="GEARBOX_RESET_REG" offset="0x04" size="32" readable="true" writable="true">
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// <info>Gearbox reset control register.</info>
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// <bitfield name="ADC_RESET" range="0" readable="false" strobe="true">
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// <info>
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// This reset is for the gearbox on the ADC data path that is used to
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// move data from one clock domain to another outside the RFDC. Write
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// a 1 to this bit to send a reset pulse to the ADC gearbox.
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// </info>
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// </bitfield>
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// <bitfield name="DAC_RESET" range="1" readable="false" strobe="true">
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// <info>
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// This reset is for the gearbox on the DAC data path that is used to
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// move data from one clock domain to another outside the RFDC. Write
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// a 1 to this bit to send a reset pulse to the DAC gearbox.
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// </info>
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// </bitfield>
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// </register>
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// </group>
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//</regmap>
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//
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//XmlParse xml_off
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