Wade Fife
845dfd4f87
Add some missing CtrlPort signal widths to ctrlport.vh. Original-commit: c9d55d870dbccbc07ca9a7afaf2e0ac64944111c
32 lines
1.0 KiB
Systemverilog
32 lines
1.0 KiB
Systemverilog
//
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// Copyright 2020 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: ctrlport.vh
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//
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// Description:
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//
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// Defines constants for the control port interface. See also
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// rfnoc_axis_ctrl_utils.vh for related AXIS-Ctrl definitions.
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//
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//---------------------------------------------------------------
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// Signal widths
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//---------------------------------------------------------------
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localparam CTRLPORT_ADDR_W = 20;
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localparam CTRLPORT_DATA_W = 32;
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localparam CTRLPORT_STS_W = 2;
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localparam CTRLPORT_PORTID_W = 10;
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localparam CTRLPORT_REM_EPID_W = 16;
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localparam CTRLPORT_BYTE_EN_W = 4;
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localparam CTRLPORT_TIME_W = 64;
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//---------------------------------------------------------------
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// Status values
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//---------------------------------------------------------------
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localparam [1:0] CTRL_STS_OKAY = 2'b00;
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localparam [1:0] CTRL_STS_CMDERR = 2'b01;
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localparam [1:0] CTRL_STS_TSERR = 2'b10;
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localparam [1:0] CTRL_STS_WARNING = 2'b11;
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