Andrew Moch
05eb1bc2f1
The rnfoc/xport section is refactored in System Verilog to allow the
following improvements
(1) CPU_W - Sets the size of the c2e and e2c pipes. This can be run
at a different clock rate than the main ethernet pipe
(2) CHDR_W - Sets the size of the v2e and e2v pipes. This can be run
at a different clock rate than the main ethernet pipe
(3) ENET_W - Sets the size of the eth_tx and eth_rx pipes.
eth_interface_tb runs traffic from e2c,e2v,v2e,c2e simultaneously
against the original xport_sv implementation, and against the new
implementation with widths of 64/128/512. A chdr_management node
info request queries the port info of the node0 in the eth_interface.
eth_ifc_synth_test.sv can be compiled with the make xsim target to test
out the size of various configurations.
Original-commit: eed4988cc266a63370a4332351d02fadedde3a3b
21 lines
689 B
Plaintext
21 lines
689 B
Plaintext
# This file contains all testbenches to exlcude from the filter
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# list discovered by run_testbenches.py
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# NOTE: Lines containing "#" are treated as a comment
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lib/rfnoc/noc_block_eq_tb
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lib/rfnoc/noc_block_ofdm_tb
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lib/rfnoc/noc_block_schmidl_cox_tb
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top/e31x/sim/dram_test
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top/n3xx/sim/arm_to_sfp_loopback
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top/n3xx/sim/aurora_loopback
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top/n3xx/sim/one_gig_eth_loopback
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top/n3xx/sim/ten_gig_eth_loopback
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top/x300/sim/x300_pcie_int
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top/n3xx/dboards/eiscat/radio/noc_block_ddc_eiscat_tb
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top/n3xx/dboards/eiscat/radio/noc_block_radio_core_eiscat_tb
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# These testbenches only work in ModelSim
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lib/axi4s_sv/axi4s_remove_bytes_tb
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lib/axi4s_sv/axi4s_add_bytes_tb
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lib/rfnoc/xport_sv/eth_interface_tb
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