Files
b210-k7-fpga/lib/ip/complex_to_magphase_int17
Wade Fife 4f99fee248 fpga: lib: Add complex_to_magphase_int17 IP
The underlying Xilinx CORDIC IP uses 2 bits for the whole part of its
(X,Y) inputs and its magnitude output. So, having 17 bits means we have
enough precision to represent the entire range of an sc16. The 16-bit
CORDIC is insufficient to cover this entire range.


Original-commit: 0d3d69493aac9239ae437b04f291c61669678606
2024-12-17 22:13:42 +01:00
..