Wade Fife
3cb320fae0
Add DEFAULT_M and DEFAULT_N parameters for rate changing cores. This allows the host to not need to configure fixed rate change cores. Original-commit: 983fad664436301c31c3bc8c81b538a41537598b
508 lines
22 KiB
Verilog
508 lines
22 KiB
Verilog
//
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// Copyright 2016 Ettus Research
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// Copyright 2018 Ettus Research, a National Instruments Company
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// Copyright 2020 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// - Implements rate change of N:M (a.k.a. M/N), handles headers automatically
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// - Note: N should always be written before M in software to prevent false rate changes
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// while the block is active
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// - User code is responsible for generating correct number of outputs per input
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// > Example: When set 1/N, after N input samples block should output 1 sample. If
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// user code's pipelining requires additional samples to "push" the 1
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// sample out, it is the user's responsibility to make the mechanism
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// (such as injecting extra samples) to do so.
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// - Will always send an integer multiple of N samples to user logic. This ensures
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// the user will not need to manually clear a "partial output sample" stuck in their
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// pipeline due to an uneven (in respect to decimation rate) number of input samples.
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// - Can optionally strobe clear_user after receiving packet with EOB
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// > enable_clear_user must be enabled via CONFIG settings register
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// > Warning: Input will be throttled until last packet has completely passed through
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// user code to prevent clearing valid data. In certain conditions, this throttling
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// can have a significant impact on throughput.
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// - Output packet size will be identical to input packet size. The only exception is
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// the final output packet, which may be shorter due to a partial input packet.
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// Limitations:
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// - Rate changes are ignored while active. Block must be cleared or packet with EOB
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// (and enable_clear_user is set) will cause new rates to be loaded.
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// - Can potentially use large amounts of block RAM when using large decimation rates
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// (greater than 2K). This occurs due to the feature that the block always sends a multiple
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// of N samples to the user. Implementing this feature requires N samples to be buffered.
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// - User code with long pipelines may need to increase HEADER_FIFOSIZE. The debug signal
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// warning_header_fifo_full is useful in determining this case.
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//
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// Settings Registers:
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// sr_n: Number of input samples per M output samples (Always write N before M)
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// sr_m: Number of output samples per N input samples
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// sr_config: 0: Enable clear_user signal.
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module axi_rate_change #(
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parameter WIDTH = 32, // Input bit width, must be a power of 2 and greater than or equal to 8.
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parameter MAX_N = 2**16,
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parameter MAX_M = 2**16,
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parameter MAXIMIZE_OUTPUT_PKT_LEN = 1,
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// Settings registers
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parameter SR_N_ADDR = 0,
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parameter SR_M_ADDR = 1,
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parameter SR_CONFIG_ADDR = 2,
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parameter SR_TIME_INCR_ADDR = 3,
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parameter DEFAULT_N = 1,
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parameter DEFAULT_M = 1
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)(
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input clk, input reset, input clear,
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output clear_user, // Strobed after end of burst. Throttles input. Useful for resetting user code between bursts.
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input [15:0] src_sid, input [15:0] dst_sid,
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input set_stb, input [7:0] set_addr, input [31:0] set_data,
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input [WIDTH-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready, input [127:0] i_tuser,
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output [WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready, output [127:0] o_tuser,
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output [WIDTH-1:0] m_axis_data_tdata, output m_axis_data_tlast, output m_axis_data_tvalid, input m_axis_data_tready,
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input [WIDTH-1:0] s_axis_data_tdata, input s_axis_data_tlast, input s_axis_data_tvalid, output s_axis_data_tready,
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// Debugging signals:
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// - Warnings indicate there may be an issue with user code.
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// - Errors mean the user code has violated a rule.
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// - Signals latch once set and block must be reset to clear.
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output reg warning_long_throttle, // In the throttle state for a "long" time.
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output reg error_extra_outputs, // User code generated extra outputs, i.e. received more than the expected M outputs.
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output reg error_drop_pkt_lockup // Drop partial packet module is not accepting data even though user code is ready.
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);
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reg [$clog2(MAX_N+1)-1:0] n = DEFAULT_N;
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reg [$clog2(MAX_M+1)-1:0] m = DEFAULT_M;
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wire [WIDTH-1:0] i_reg_tdata;
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wire i_reg_tvalid, i_reg_tready, i_reg_tlast;
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wire i_reg_tvalid_int, i_reg_tready_int, i_reg_tlast_int;
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reg throttle = 1'b1, first_header, partial_first_word;
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reg [15:0] word_cnt_div_n;
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reg [$clog2(MAX_N+1)-1:0] word_cnt_div_n_frac = 1;
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reg [$clog2(MAX_N+1)-1:0] in_pkt_cnt = 1;
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reg send_done;
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reg rate_changed;
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/********************************************************
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** Settings Registers
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********************************************************/
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wire [$clog2(MAX_N+1)-1:0] sr_n;
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wire n_changed;
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setting_reg #(.my_addr(SR_N_ADDR), .width($clog2(MAX_N+1)), .at_reset(DEFAULT_N)) set_n (
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.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
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.out(sr_n), .changed(n_changed));
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wire [$clog2(MAX_M+1)-1:0] sr_m;
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wire m_changed;
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setting_reg #(.my_addr(SR_M_ADDR), .width($clog2(MAX_M+1)), .at_reset(DEFAULT_M)) set_m (
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.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
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.out(sr_m), .changed(m_changed));
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wire sr_config;
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wire enable_clear_user; // Enable strobing clear_user between bursts.
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setting_reg #(.my_addr(SR_CONFIG_ADDR), .width(1), .at_reset(1'b1)) set_config (
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.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
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.out(sr_config), .changed());
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assign enable_clear_user = sr_config;
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// Time increment in ticks per M samples
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wire [$clog2(MAX_N+1)-1:0] sr_time_incr;
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reg [$clog2(MAX_N+1)-1:0] time_incr;
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setting_reg #(
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.my_addr(SR_TIME_INCR_ADDR), .width($clog2(MAX_N+1)), .at_reset(0)
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) set_time_incr (
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.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
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.out(sr_time_incr), .changed());
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/********************************************************
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** Header, word count FIFOs
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** - Header provides VITA Time and payload length for
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** output packets
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** - Word count provides a normalized count for the
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** output state machine to know when it has consumed
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** the final input sample in a burst.
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********************************************************/
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// Decode input header
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wire [127:0] i_reg_tuser;
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wire has_time_in, eob_in, eob_in_header;
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wire [15:0] payload_length_in;
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reg [15:0] payload_length_out;
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wire [63:0] vita_time_in;
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cvita_hdr_decoder cvita_hdr_decoder_in_header (
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.header(i_reg_tuser), .pkt_type(), .eob(eob_in_header),
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.has_time(has_time_in), .seqnum(), .length(), .payload_length(payload_length_in),
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.src_sid(), .dst_sid(), .vita_time(vita_time_in));
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assign eob_in = eob_in_header | rate_changed;
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reg [15:0] word_cnt_div_n_tdata;
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wire [15:0] word_cnt_div_n_fifo_tdata;
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reg word_cnt_div_n_tvalid;
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wire word_cnt_div_n_tready, word_cnt_div_n_fifo_tvalid, word_cnt_div_n_fifo_tready;
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axi_fifo #(.WIDTH(16), .SIZE(0)) axi_fifo_word_cnt (
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.clk(clk), .reset(reset), .clear(clear),
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.i_tdata(word_cnt_div_n_tdata), .i_tvalid(word_cnt_div_n_tvalid), .i_tready(word_cnt_div_n_tready),
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.o_tdata(word_cnt_div_n_fifo_tdata), .o_tvalid(word_cnt_div_n_fifo_tvalid), .o_tready(word_cnt_div_n_fifo_tready),
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.space(), .occupied());
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/********************************************************
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** Register input stream
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** - Upsteam will be throttled when clearing user logic
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********************************************************/
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// Input register with header
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axi_fifo_flop #(.WIDTH(WIDTH+1+128)) axi_fifo_flop_input (
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.clk(clk), .reset(reset), .clear(clear),
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.i_tdata({i_tlast,i_tdata,i_tuser}), .i_tvalid(i_tvalid), .i_tready(i_tready),
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.o_tdata({i_reg_tlast,i_reg_tdata,i_reg_tuser}), .o_tvalid(i_reg_tvalid_int), .o_tready(i_reg_tready),
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.space(), .occupied());
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assign i_reg_tready = i_reg_tready_int & word_cnt_div_n_tready & ~throttle;
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assign i_reg_tvalid = i_reg_tvalid_int & word_cnt_div_n_tready & ~throttle;
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// Assert AXI Drop Partial Packet's i_tlast every N samples, which is used to detect and drop
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// partial output samples.
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assign i_reg_tlast_int = (word_cnt_div_n_frac == n) | (eob_in & i_reg_tlast);
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/********************************************************
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** Input state machine
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********************************************************/
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reg [1:0] input_state;
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localparam RECV_INIT = 0;
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localparam RECV = 1;
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localparam RECV_WAIT_FOR_SEND_DONE = 2;
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always @(posedge clk) begin
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if (reset | clear) begin
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n <= DEFAULT_N;
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m <= DEFAULT_M;
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rate_changed <= 1'b0;
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first_header <= 1'b1;
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partial_first_word <= 1'b1;
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payload_length_out <= 'd0;
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word_cnt_div_n <= 0;
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word_cnt_div_n_frac <= 1;
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throttle <= 1'b1;
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word_cnt_div_n_tvalid <= 1'b0;
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word_cnt_div_n_tdata <= 'd0;
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input_state <= RECV_INIT;
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end else begin
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if (word_cnt_div_n_tvalid & word_cnt_div_n_tready) begin
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word_cnt_div_n_tvalid <= 1'b0;
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end
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// Input state machine
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case (input_state)
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RECV_INIT : begin
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n <= sr_n;
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m <= sr_m;
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// Default time increment to sr_n value to preserve default behavior
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time_incr <= sr_time_incr == 0 ? sr_n : sr_time_incr;
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rate_changed <= 1'b0;
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first_header <= 1'b1;
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partial_first_word <= 1'b1;
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payload_length_out <= 'd0;
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word_cnt_div_n <= 0;
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word_cnt_div_n_frac <= 1;
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if (i_reg_tvalid_int & word_cnt_div_n_tready) begin
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throttle <= 1'b0;
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input_state <= RECV;
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end
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end
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// Logic used by the RECV state to track several variables:
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// word_cnt_div_n: Number of words received divided by n.
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// Needed for tracking final sample in a burst.
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// word_cnt_div_n_frac: Used to increment word_cnt_div_n. Can be
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// thought of as the fractional part of
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// word_cnt_div_n.
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// in_pkt_cnt: Similar to in_word_cnt, but for packets. Used
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// to determine when a group of N packets has been
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// received to store the next header.
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// first_header: We only use the header from the first packet in
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// a group of N packets (this greatly reduces
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// the header FIFO size).
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RECV : begin
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// If rate changed, force a EOB.
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if (m_changed) begin
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rate_changed <= 1'b1;
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end
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if (i_reg_tvalid & i_reg_tready) begin
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// Track the number of words sent to the user divided by N.
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// At the end of a burst, this value is forwarded to the output
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// state machine and used to determine when the final sample has
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// arrived from the user code.
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if (word_cnt_div_n_frac == n) begin
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word_cnt_div_n <= word_cnt_div_n + 1;
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word_cnt_div_n_frac <= 1;
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end else begin
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word_cnt_div_n_frac <= word_cnt_div_n_frac + 1;
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end
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// Use payload length from first packet
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first_header <= 1'b0;
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if (first_header) begin
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payload_length_out <= payload_length_in;
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end else if (MAXIMIZE_OUTPUT_PKT_LEN) begin
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if (payload_length_out < payload_length_in) begin
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payload_length_out <= payload_length_in;
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end
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end
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// Track when at least N input samples have been received in this burst
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if (partial_first_word & (word_cnt_div_n_frac == n)) begin
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partial_first_word <= 1'b0;
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end
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// Burst ended before we received enough samples to form
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// at least one full output sample.
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// Note: axi_drop_partial_packet automatically handles
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// dropping the partial sample.
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if (i_reg_tlast & eob_in & partial_first_word) begin
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input_state <= RECV_INIT;
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end else begin
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if (i_reg_tlast) begin
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// At the end of a burst, forward the number of words divided by N to
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// the output state machine via a FIFO. This allows the output state
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// machine to know when it has received the final output word.
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// We use a FIFO in case the bursts are very small and we
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// need to store several of these values.
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if (eob_in) begin
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word_cnt_div_n_tdata <= word_cnt_div_n + (word_cnt_div_n_frac == n);
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word_cnt_div_n_tvalid <= 1'b1;
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throttle <= 1'b1;
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if (enable_clear_user) begin
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input_state <= RECV_WAIT_FOR_SEND_DONE;
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end else begin
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input_state <= RECV_INIT;
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end
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end
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end
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end
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end
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end
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// Wait until last sample has been output and user logic is cleared
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// WARNING: This can be a huge bubble state! However, since it only happens with
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// EOBs, it should be infrequent.
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RECV_WAIT_FOR_SEND_DONE : begin
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if (send_done) begin
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input_state <= RECV_INIT;
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end
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end
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default : begin
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input_state <= RECV_INIT;
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end
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endcase
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end
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end
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assign clear_user = send_done & enable_clear_user;
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/********************************************************
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** AXI Drop Partial Packet (to user)
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** - Enforces sending integer multiple of N samples
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** to user
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********************************************************/
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axi_drop_partial_packet #(
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.WIDTH(WIDTH+1),
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.HOLD_LAST_WORD(1),
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.MAX_PKT_SIZE(MAX_N),
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.SR_PKT_SIZE_ADDR(SR_N_ADDR),
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.DEFAULT_PKT_SIZE(DEFAULT_N))
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axi_drop_partial_packet (
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.clk(clk), .reset(reset), .clear(clear | send_done),
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.flush(word_cnt_div_n_tvalid & word_cnt_div_n_tready), // Flush on EOB
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.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
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.i_tdata({i_reg_tlast,i_reg_tdata}), .i_tvalid(i_reg_tvalid), .i_tlast(i_reg_tlast_int), .i_tready(i_reg_tready_int),
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.o_tdata({m_axis_data_tlast,m_axis_data_tdata}), .o_tvalid(m_axis_data_tvalid), .o_tlast(/* Unused */), .o_tready(m_axis_data_tready));
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/********************************************************
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** Output state machine
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********************************************************/
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reg [1:0] output_state;
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localparam SEND_INIT = 0;
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localparam SEND = 1;
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wire [WIDTH-1:0] o_reg_tdata;
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wire [127:0] o_reg_tuser;
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wire o_reg_tvalid, o_reg_tready, o_reg_tlast, o_reg_tlast_int;
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reg [15:0] out_payload_cnt = (WIDTH/8);
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reg [15:0] word_cnt_div_m;
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reg [$clog2(MAX_M+1)-1:0] word_cnt_div_m_frac = 1;
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reg [$clog2(MAX_M+1)-1:0] out_pkt_cnt = 1;
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// End of burst tracking. Compare the number of words sent to the user divided by N
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// to the number of words received from the user divided by M. When they equal each other
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// then we have received the last word from the user in this burst.
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// Note: Using word_cnt_div_n_fifo_tdata to make sure the last word is identified before
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// it has been consumed.
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wire last_word_in_burst = word_cnt_div_n_fifo_tvalid &
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(word_cnt_div_m == word_cnt_div_n_fifo_tdata) &
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(word_cnt_div_m_frac == m);
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always @(posedge clk) begin
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if (reset | clear) begin
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word_cnt_div_m <= 1;
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word_cnt_div_m_frac <= 1;
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out_payload_cnt <= (WIDTH/8);
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send_done <= 1'b0;
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output_state <= SEND_INIT;
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end else begin
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// Track
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case (output_state)
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SEND_INIT : begin
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word_cnt_div_m <= 1;
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word_cnt_div_m_frac <= 1;
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out_payload_cnt <= (WIDTH/8);
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send_done <= 1'b0;
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output_state <= SEND;
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end
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SEND : begin
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if (o_reg_tvalid & o_reg_tready) begin
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if (o_reg_tlast) begin
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// Track number of samples from user to set tlast
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out_payload_cnt <= (WIDTH/8);
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end else begin
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out_payload_cnt <= out_payload_cnt + (WIDTH/8);
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end
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// Track number of words consumed divided by M. This is used
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// in conjunction with word_cnt_div_n to determine when we have received
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// the last word in a burst from the user.
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if (word_cnt_div_m_frac == m) begin
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word_cnt_div_m <= word_cnt_div_m + 1;
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word_cnt_div_m_frac <= 1;
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end else begin
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word_cnt_div_m_frac <= word_cnt_div_m_frac + 1;
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end
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if (last_word_in_burst) begin
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send_done <= 1'b1;
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output_state <= SEND_INIT;
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end
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end
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end
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default : begin
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output_state <= SEND_INIT;
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end
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endcase
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end
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end
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// Only pop this FIFO at EOB.
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assign word_cnt_div_n_fifo_tready = o_reg_tvalid & o_reg_tready & last_word_in_burst;
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/********************************************************
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** Adjust VITA time
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********************************************************/
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localparam VT_INIT = 0;
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localparam VT_INCREMENT = 1;
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reg vt_state;
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reg has_time_out, has_time_clear;
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reg [63:0] vita_time_out, vita_time_accum;
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always @(posedge clk) begin
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if (reset | clear) begin
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vt_state <= VT_INIT;
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end else begin
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case (vt_state)
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VT_INIT : begin
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has_time_clear <= 1'b0;
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if (i_reg_tvalid & i_reg_tready & first_header) begin
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|
vita_time_out <= vita_time_in;
|
|
vita_time_accum <= vita_time_in;
|
|
has_time_out <= has_time_in;
|
|
vt_state <= VT_INCREMENT;
|
|
end
|
|
end
|
|
VT_INCREMENT : begin
|
|
// Stop sending vita time if user does not send vita time
|
|
if (i_reg_tvalid & ~has_time_in) begin
|
|
has_time_clear <= 1'b1;
|
|
end
|
|
if (o_reg_tvalid & o_reg_tready) begin
|
|
if (o_reg_tlast) begin
|
|
if (has_time_clear) begin
|
|
has_time_out <= 1'b0;
|
|
end
|
|
vita_time_out <= vita_time_accum + time_incr;
|
|
end
|
|
vita_time_accum <= vita_time_accum + time_incr;
|
|
if (last_word_in_burst) begin
|
|
vt_state <= VT_INIT;
|
|
end
|
|
end
|
|
end
|
|
default : begin
|
|
vt_state <= VT_INIT;
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
|
|
// Create output header
|
|
cvita_hdr_encoder cvita_hdr_encoder (
|
|
.pkt_type(2'd0), .eob(last_word_in_burst), .has_time(has_time_out),
|
|
.seqnum(12'd0), .payload_length(16'd0), // Not needed, handled by AXI Wrapper
|
|
.src_sid(src_sid), .dst_sid(dst_sid),
|
|
.vita_time(vita_time_out),
|
|
.header(o_reg_tuser));
|
|
|
|
/********************************************************
|
|
** Register input stream from user and output stream
|
|
********************************************************/
|
|
assign o_reg_tlast = o_reg_tlast_int |
|
|
// End of packet
|
|
(out_payload_cnt == payload_length_out) |
|
|
// EOB, could be a partial packet
|
|
last_word_in_burst;
|
|
|
|
axi_fifo_flop #(.WIDTH(WIDTH+1)) axi_fifo_flop_from_user_0 (
|
|
.clk(clk), .reset(reset), .clear(clear),
|
|
// FIXME: If user asserts tlast at the wrong time, it likely causes a deadlock. For now ignore tlast.
|
|
//.i_tdata({s_axis_data_tlast,s_axis_data_tdata}), .i_tvalid(s_axis_data_tvalid), .i_tready(s_axis_data_tready),
|
|
.i_tdata({1'b0,s_axis_data_tdata}), .i_tvalid(s_axis_data_tvalid), .i_tready(s_axis_data_tready),
|
|
.o_tdata({o_reg_tlast_int,o_reg_tdata}), .o_tvalid(o_reg_tvalid), .o_tready(o_reg_tready),
|
|
.space(), .occupied());
|
|
|
|
// Output register with header
|
|
axi_fifo_flop #(.WIDTH(WIDTH+1+128)) axi_fifo_flop_output (
|
|
.clk(clk), .reset(reset), .clear(clear),
|
|
.i_tdata({o_reg_tlast,o_reg_tdata,o_reg_tuser}), .i_tvalid(o_reg_tvalid), .i_tready(o_reg_tready),
|
|
.o_tdata({o_tlast,o_tdata,o_tuser}), .o_tvalid(o_tvalid), .o_tready(o_tready),
|
|
.space(), .occupied());
|
|
|
|
/********************************************************
|
|
** Error / warning signals
|
|
********************************************************/
|
|
reg [23:0] counter_header_fifo_full, counter_throttle, counter_drop_pkt_lockup;
|
|
reg [2:0] counter_header_fifo_empty;
|
|
always @(posedge clk) begin
|
|
if (reset) begin
|
|
warning_long_throttle <= 1'b0;
|
|
error_extra_outputs <= 1'b0;
|
|
error_drop_pkt_lockup <= 1'b0;
|
|
counter_throttle <= 0;
|
|
counter_header_fifo_full <= 0;
|
|
counter_drop_pkt_lockup <= 0;
|
|
counter_header_fifo_empty <= 0;
|
|
end else begin
|
|
// In throttle state for a "long" time
|
|
if (throttle) begin
|
|
counter_throttle <= counter_throttle + 1;
|
|
if (counter_throttle == 2**24-1) begin
|
|
warning_long_throttle <= 1'b1;
|
|
end
|
|
end else begin
|
|
counter_throttle <= 0;
|
|
end
|
|
// More than M outputs per N inputs
|
|
if (word_cnt_div_n_fifo_tvalid & (word_cnt_div_m > word_cnt_div_n_fifo_tdata)) begin
|
|
error_extra_outputs <= 1'b1;
|
|
end
|
|
// Bad internal state. AXI drop partial packet is in a lockup condition.
|
|
if (~i_reg_tready_int & m_axis_data_tready) begin
|
|
counter_drop_pkt_lockup <= counter_drop_pkt_lockup + 1;
|
|
if (counter_drop_pkt_lockup == 2**24-1) begin
|
|
error_drop_pkt_lockup <= 1'b1;
|
|
end
|
|
end else begin
|
|
counter_drop_pkt_lockup <= 0;
|
|
end
|
|
end
|
|
end
|
|
|
|
endmodule
|