Andrew Moch
55881469ac
This fixes the rfnoc_null_src_sink, chdr_crossbar_nxn, and chdr_stream_endpoint blocks so that wider CHDR widths are properly supported. It also updates PkgChdrBfm to able to properly test these blocks. The testbenches have been updated to test both 64 and 512-bit widths. Original-commit: 3af8dcaacfa4bf36dcae3bdbf0b353385b7063c6
46 lines
1.4 KiB
Makefile
46 lines
1.4 KiB
Makefile
#
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# Copyright 2019 Ettus Research, A National Instruments Company
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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#-------------------------------------------------
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# Top-of-Makefile
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#-------------------------------------------------
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# Define BASE_DIR to point to the "top" dir
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BASE_DIR = $(abspath ../../../../top)
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# Include viv_sim_preamble after defining BASE_DIR
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include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
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#-------------------------------------------------
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# Design Specific
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#-------------------------------------------------
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# Include makefiles and sources for the DUT and its dependencies
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include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/crossbar/Makefile.srcs
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DESIGN_SRCS += $(abspath \
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$(RFNOC_CORE_SRCS) \
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$(RFNOC_XBAR_SRCS) \
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)
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#-------------------------------------------------
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# Testbench Specific
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#-------------------------------------------------
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SIM_TOP = chdr_stream_endpoint_all_tb
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SIM_SRCS = \
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$(abspath lossy_xport_model.v) \
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$(abspath chdr_stream_endpoint_tb.sv) \
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$(abspath chdr_stream_endpoint_all_tb.sv) \
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#-------------------------------------------------
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# Bottom-of-Makefile
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#-------------------------------------------------
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# Include all simulator specific makefiles here
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# Each should define a unique target to simulate
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# e.g. xsim, vsim, etc and a common "clean" target
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include $(BASE_DIR)/../tools/make/viv_simulator.mak
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