Wade Fife
81bb2ae28f
This adds the ability to do IP generation and FPGA builds using the --jobs (-j) option with Make. For example, rather than generating each IP one after another, you can generate up to N at a time using N Vivado instances. This greatly reduces the IP generation time. Similarly, parallel jobs can be used to easily build different FPGA variants simultaneously. Because FPGA builds can consume a lot of memory, care must be taken to ensure that the number of jobs is not too high for the amount of memory available. New IP make targets were added for each USRP so that IP can be built separately from the FPGA. The IP targets are now a dependency on each FPGA target. For example, you can generate the IP for X310 using 4 parallel jobs using the following command: make -j4 X310_IP Or, build two X310 bitstreams simultaneously: make -j2 X310_XG X310_HG Original-commit: 4b03e237a96ee277eefff257d65b08708c38662c
155 lines
5.2 KiB
Makefile
155 lines
5.2 KiB
Makefile
#
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# Copyright 2012-2016 Ettus Research LLC
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#
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# NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target
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##-------------------
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##USRP X3X0 FPGA Help
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##-------------------
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##Usage:
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## make <Targets> <Options>
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##
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##Output:
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## build/usrp_<product>_fpga_<image_type>.bit: Configuration bitstream with header
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## build/usrp_<product>_fpga_<image_type>.bin: Configuration bitstream without header
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## build/usrp_<product>_fpga_<image_type>.lvbitx: Configuration bitstream for PCIe (NI-RIO)
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## build/usrp_<product>_fpga_<image_type>.rpt: Build report (includes utilization and timing summary)
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# Debug Options
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# Uncomment the following line to add a debug UART on GPIO 10 & 11
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#OPTIONS += DEBUG_UART=1
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CREATE_LVBITX=python ../../lib/io_port2/create-lvbitx.py
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GIGE_DEFS=BUILD_1G=1 SFP0_1GBE=1 SFP1_1GBE=1 $(OPTIONS)
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HG_DEFS=BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 SFP1_10GBE=1 $(OPTIONS)
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XG_DEFS=BUILD_10G=1 SFP0_10GBE=1 SFP1_10GBE=1 $(OPTIONS)
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HA_DEFS=BUILD_1G=1 BUILD_AURORA=1 SFP0_1GBE=1 SFP1_AURORA=1 $(OPTIONS)
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XA_DEFS=BUILD_10G=1 BUILD_AURORA=1 SFP0_10GBE=1 SFP1_AURORA=1 $(OPTIONS)
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# Set build option (check RTL, run synthesis, or do a full build)
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ifndef TARGET
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ifdef CHECK
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TARGET = rtl
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else ifdef SYNTH
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TARGET = synth
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else
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TARGET = bin
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endif
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endif
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TOP ?= x300
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DEFAULT_IMAGE_CORE_FILE_X300=x300_rfnoc_image_core.v
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DEFAULT_IMAGE_CORE_FILE_X310=x310_rfnoc_image_core.v
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DEFAULT_EDGE_FILE_X300=$(abspath x300_static_router.hex)
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DEFAULT_EDGE_FILE_X310=$(abspath x310_static_router.hex)
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# vivado_build($1=Device, $2=Definitions)
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vivado_build = make -f Makefile.x300.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_$1) DEFAULT_EDGE_FILE=$(DEFAULT_EDGE_FILE_$1)
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vivado_ip = make -f Makefile.x300.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_$1) DEFAULT_EDGE_FILE=$(DEFAULT_EDGE_FILE_$1)
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# post_build($1=Device, $2=Option)
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ifeq ($(TARGET),bin)
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post_build = @\
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mkdir -p build; \
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echo "Exporting bitstream files..."; \
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cp build-$(1)_$(2)/x300.bin build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bin; \
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cp build-$(1)_$(2)/x300.bit build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \
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echo "Generating LVBITX..."; \
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$(CREATE_LVBITX) --input-bin=build-$(1)_$(2)/x300.bin --output-lvbitx=build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).lvbitx --device="USRP $(1)" x3x0_base.lvbitx; \
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cp -f x3x0_base.lvbitx build/`echo $(1) | tr A-Z a-z`.lvbitx_base; \
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echo "Exporting build report..."; \
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cp build-$(1)_$(2)/build.rpt build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).rpt; \
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echo "Build DONE ... $(1)_$(2)";
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else
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post_build = @echo "Skipping bitfile export."
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endif
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##
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##Supported Targets
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##-----------------
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##all: X300_HG X310_HG X300_XG X310_XG (Default target)
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all: X300_HG X310_HG X300_XG X310_XG
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##X300_IP: Build IP for X300 only.
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X300_IP:
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+$(call vivado_ip,X300,$(HG_DEFS) X300=1)
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##X310_IP: Build IP for X310 only.
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X310_IP:
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+$(call vivado_ip,X310,$(HG_DEFS) X310=1)
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##X310_1G: 1GigE on both SFP+ ports.
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X310_1G: X310_IP
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$(call vivado_build,X310,$(GIGE_DEFS) X310=1)
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$(call post_build,X310,1G)
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##X300_1G: 1GigE on both SFP+ ports.
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X300_1G: X300_IP
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$(call vivado_build,X300,$(GIGE_DEFS) X300=1)
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$(call post_build,X300,1G)
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##X310_HG: 1GigE on SFP+ Port0, 10Gig on SFP+ Port1.
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X310_HG: X310_IP
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$(call vivado_build,X310,$(HG_DEFS) X310=1)
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$(call post_build,X310,HG)
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##X300_HG: 1GigE on SFP+ Port0, 10Gig on SFP+ Port1.
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X300_HG: X300_IP
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$(call vivado_build,X300,$(HG_DEFS) X300=1)
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$(call post_build,X300,HG)
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##X310_XG: 10GigE on both SFP+ ports.
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X310_XG: X310_IP
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$(call vivado_build,X310,$(XG_DEFS) X310=1)
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$(call post_build,X310,XG)
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##X300_XG: 10GigE on both SFP+ ports.
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X300_XG: X300_IP
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$(call vivado_build,X300,$(XG_DEFS) X300=1)
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$(call post_build,X300,XG)
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##X310_HA: 1Gig on SFP+ Port0, Aurora on SFP+ Port1.
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X310_HA: X310_IP
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$(call vivado_build,X310,$(HA_DEFS) X310=1)
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$(call post_build,X310,HA)
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##X300_HA: 1Gig on SFP+ Port0, Aurora on SFP+ Port1.
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X300_HA: X300_IP
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$(call vivado_build,X300,$(HA_DEFS) X300=1)
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$(call post_build,X300,HA)
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##X310_XA: 10Gig on SFP+ Port0, Aurora on SFP+ Port1.
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X310_XA: X310_IP
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$(call vivado_build,X310,$(XA_DEFS) X310=1)
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$(call post_build,X310,XA)
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##X300_XA: 10Gig on SFP+ Port0, Aurora on SFP+ Port1.
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X300_XA: X300_IP
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$(call vivado_build,X300,$(XA_DEFS) X300=1)
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$(call post_build,X300,XA)
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clean: ##Clean up all target build outputs.
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@echo "Cleaning targets..."
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@rm -rf build-X3*_*
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@rm -rf build
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cleanall: ##Clean up all target and ip build outputs.
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@echo "Cleaning targets and IP..."
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@rm -rf build-ip
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@rm -rf build-X3*_*
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@rm -rf build
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help: ##Show this help message.
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@grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//'
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##
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##Supported Options
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##-----------------
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##GUI=1 Launch the build in the Vivado GUI.
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##CHECK=1 Launch the syntax checker instead of building a bitfile.
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##SYNTH=1 Launch the build but stop after synthesis.
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##TOP=<module> Specify a top module for syntax checking. (Optional. Default is the bitfile top)
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.PHONY: all clean cleanall help
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