Wade Fife
032b9677aa
The NET_CHDR_W parameter tells the transport adapter what CHDR width is used in transport packets, such as Ethernet packets. By default the CHDR width used by the transport and RFNoC core will be the same. The NET_CHDR_W parameter can be used in situations where the RFNoC core expects a CHDR width from the transport adapter that is different from that used over the network. In this situation, the transport adapter will rewrite the CHDR packets so that each side gets the expected CHDR width. Original-commit: a9e49b7c587ef778ee0fe327e8bdcb15e0b0fc95
498 lines
17 KiB
Systemverilog
498 lines
17 KiB
Systemverilog
//
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// Copyright 2020 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: eth_ipv4_chdr_adapter
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// Description: A generic transport adapter module that can be used in
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// a variety of transports. It does the following:
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// - Exposes a configuration port for mgmt packets to configure the node
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// - Implements a return-address map for packets with metadata other than
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// the CHDR. Additional metadata can be passed as a tuser to this module
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// which will store it in a map indexed by the SrcEPID in a management
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// packet. For all returning packets, the metadata will be looked up in
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// the map and attached as the outgoing tuser.
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// - Implements a loopback path for node-info discovery
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//
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// Parameters:
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// - PROTOVER: RFNoC protocol version {8'd<major>, 8'd<minor>}
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// - CPU_FIFO_SIZE: Log2 of the FIFO depth (in bytes) for the CPU egress path
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// - CHDR_FIFO_SIZE: Log2 of the FIFO depth (in bytes) for the CHDR egress path
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// - RT_TBL_SIZE: Log2 of the depth of the return-address routing table
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// - NODE_INST: The node type to return for a node-info discovery
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// - DROP_UNKNOWN_MAC: Drop packets not addressed to us?
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// - DROP_MIN_PACKET: Drop packets smaller than 64 bytes?
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// - PREAMBLE_BYTES: Number of bytes of Preamble expected
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// - ADD_SOF: Add a SOF indication into the tuser field of the e2c path.
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// If false use TKEEP instead of USER.
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// - SYNC: Set if the CPU clock domain (c2e, e2c) is not the same as the
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// Ethernet clock domain (eth_rx, eth_tx).
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// - ENET_W: Width of the link to the Ethernet MAC
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// - CPU_W: Width of the CPU interface
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// - CHDR_W: CHDR width used by RFNoC on the FPGA
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// - NET_CHDR_W: CHDR width used over the network connection
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//
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// Signals:
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// - device_id : The ID of the device that has instantiated this module
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// - eth_rx : The input Ethernet stream from the MAC
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// - eth_tx : The output Ethernet stream to the MAC
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// - v2e : The input CHDR stream from the rfnoc infrastructure
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// - e2v : The output CHDR stream to the rfnoc infrastructure
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// - c2e : The input Ethernet stream from the CPU
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// - e2c : The output Ethernet stream to the CPU
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// - my_mac: The Ethernet (MAC) address of this endpoint
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// - my_ip: The IPv4 address of this endpoint
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// - my_udp_chdr_port: The UDP port allocated for CHDR traffic on this endpoint
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//
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module eth_ipv4_chdr_adapter #(
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logic [15:0] PROTOVER = {8'd1, 8'd0},
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int CPU_FIFO_SIZE = $clog2(8*1024),
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int CHDR_FIFO_SIZE = $clog2(8*1024),
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int RT_TBL_SIZE = 6,
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int NODE_INST = 0,
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bit DROP_UNKNOWN_MAC = 0,
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bit DROP_MIN_PACKET = 0,
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int PREAMBLE_BYTES = 6,
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bit ADD_SOF = 1,
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bit SYNC = 0,
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int ENET_W = 64,
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int CPU_W = 64,
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int CHDR_W = 64,
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int NET_CHDR_W = CHDR_W
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)(
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// Device info
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input logic [15:0] device_id,
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// Device addresses
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input logic [47:0] my_mac,
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input logic [31:0] my_ip,
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input logic [15:0] my_udp_chdr_port,
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input logic [15:0] my_pause_set,
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input logic [15:0] my_pause_clear,
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output logic chdr_dropped,
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output logic cpu_dropped,
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// Ethernet MAC (domain: eth_rx.clk)
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output logic eth_pause_req,
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AxiStreamIf.master eth_tx, // tUser = {1'b0,trailing bytes};
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AxiStreamIf.slave eth_rx, // tUser = {error,trailing bytes};
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// CHDR router interface (eth_rx.clk)
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AxiStreamIf.master e2v, // tUser = {*not used*};
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AxiStreamIf.slave v2e, // tUser = {*not used*};
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// CPU DMA
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// (domain: e2c.clk if SYNC=0, else eth_rx.clk)
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AxiStreamIf.master e2c, // tUser = {sof,trailing bytes};
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// (domain: c2e.clk if SYNC=0, else eth_rx.clk)
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AxiStreamIf.slave c2e // tUser = {1'b0,trailing bytes};
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);
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`include "../core/rfnoc_chdr_utils.vh"
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`include "../core/rfnoc_chdr_internal_utils.vh"
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`include "../../axi4s_sv/axi4s.vh"
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localparam ENET_USER_W = $clog2(ENET_W/8)+1;
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localparam CPU_USER_W = $clog2(CPU_W/8)+1;
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localparam CHDR_USER_W = $clog2(CHDR_W/8);
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localparam MAX_PACKET_BYTES = 2**16;
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localparam DEBUG = 0;
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`include "eth_constants.vh"
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// tUser = {error,trailing_bytes}
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AxiStreamIf #(.DATA_WIDTH(ENET_W),.USER_WIDTH(ENET_USER_W),.TKEEP(0)) eth_rx1(eth_rx.clk,eth_rx.rst);
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//---------------------------------------
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// E2V and E2C DEMUX
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//---------------------------------------
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// tUser = {*not used*}
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AxiStreamIf #(.DATA_WIDTH(ENET_W),.TKEEP(0),.TUSER(0)) e2v1(eth_rx.clk,eth_rx.rst);
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// tUser = {*not used*}
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AxiStreamIf #(.DATA_WIDTH(CHDR_W),.TKEEP(0),.TUSER(0)) e2v2(e2v.clk,e2v.rst);
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// tUser = {*not used*}
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AxiStreamIf #(.DATA_WIDTH(CHDR_W),.TKEEP(0),.TUSER(0)) e2v3(e2v.clk,e2v.rst);
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// tUser = {1'b0,trailing bytes}
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AxiStreamIf #(.DATA_WIDTH(ENET_W),.USER_WIDTH(ENET_USER_W),.TKEEP(0)) e2c1(eth_rx.clk,eth_rx.rst);
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// tUser = {sof,trailing bytes} IF ADD_SOF
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AxiStreamIf #(.DATA_WIDTH(CPU_W),.USER_WIDTH(CPU_USER_W),
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.TKEEP(!ADD_SOF), .TUSER(ADD_SOF))
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e2c2(e2c.clk,e2c.rst);
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// The older implementation connected with tUser containing trailing bytes
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// The newer implementation brings in TKEEP
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// inside this block we expect trailing bytes.
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always_comb begin
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`AXI4S_ASSIGN(eth_rx1,eth_rx)
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if (eth_rx.TKEEP) begin
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eth_rx1.tuser = {eth_rx.tuser[ENET_USER_W-1],eth_rx.keep2trailing(eth_rx.tkeep)};
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end
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end
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// Ethernet sink. Inspects packet and dispatches
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// to the correct port.
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eth_ipv4_chdr_dispatch #(
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.CPU_FIFO_SIZE (CPU_FIFO_SIZE),
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.CHDR_FIFO_SIZE (CHDR_FIFO_SIZE),
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.PREAMBLE_BYTES (PREAMBLE_BYTES),
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.MAX_PACKET_BYTES (MAX_PACKET_BYTES),
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.DROP_UNKNOWN_MAC (DROP_UNKNOWN_MAC),
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.DROP_MIN_PACKET (DROP_MIN_PACKET),
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.ENET_W (ENET_W)
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) eth_dispatch_i (
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.eth_pause_req (eth_pause_req),
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.eth_rx (eth_rx1),
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.e2v (e2v1),
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.e2c (e2c1),
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.my_mac (my_mac),
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.my_ip (my_ip),
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.my_udp_chdr_port (my_udp_chdr_port),
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.my_pause_set (my_pause_set),
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.my_pause_clear (my_pause_clear),
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.chdr_dropped (chdr_dropped),
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.cpu_dropped (cpu_dropped)
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);
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//---------------------------------------
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// E2C Path
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//---------------------------------------
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if (ENET_W != CPU_W || !SYNC) begin : gen_e2c_width_conv
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axi4s_width_conv #(.I_USER_TRAILING_BYTES(1),.O_USER_TRAILING_BYTES(ADD_SOF),.SYNC_CLKS(0))
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e2c_width_conv (.i(e2c1), .o(e2c2));
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end else begin : gen_e2c_width_match
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always_comb begin : e2c_assign
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`AXI4S_ASSIGN(e2c2,e2c1)
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end
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end
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if (ADD_SOF) begin : add_sof
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logic sof = 1'b1;
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// Add SOF
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always_ff @(posedge e2c.clk) begin : cpu3_find_sof
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if (e2c.rst) begin
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sof <= 1'b1;
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end else if (e2c2.tvalid && e2c2.tready) begin
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sof <= e2c2.tlast;
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end
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end
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always_comb begin : e2c2_sof_assign
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`AXI4S_ASSIGN(e2c,e2c2)
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e2c.tuser = {sof,e2c2.tuser[CPU_USER_W-2:0]};
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end
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end else begin : no_sof
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if (DEBUG) begin
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`AXI4S_DEBUG_ASSIGN(e2c,e2c2)
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end else begin
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always_comb begin : e2c_nodebug_assign
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`AXI4S_ASSIGN(e2c,e2c2)
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end
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end
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end
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//---------------------------------------
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// E2V Path
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//---------------------------------------
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if (ENET_W != CHDR_W || !SYNC) begin : gen_e2v_width_conv
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// assumes full words on input
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axi4s_width_conv #(.SYNC_CLKS(0))
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e2v_width_conv (.i(e2v1), .o(e2v2));
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end else begin : gen_e2v_width_match
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always_comb begin : e2v_assign
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`AXI4S_ASSIGN(e2v2,e2v1)
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end
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end
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//---------------------------------------
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// CHDR Transport Adapter
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//---------------------------------------
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// tUser = {*not used*}
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AxiStreamIf #(.DATA_WIDTH(CHDR_W),.USER_WIDTH(ENET_USER_W),.TKEEP(0))
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v2e1D(v2e.clk,v2e.rst);
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// tUser = {*not used*}
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AxiStreamIf #(.DATA_WIDTH(CHDR_W),.USER_WIDTH(ENET_USER_W),.TKEEP(0))
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v2e1(v2e.clk,v2e.rst);
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// tUser = {*not used*}
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AxiStreamIf #(.DATA_WIDTH(ENET_W),.USER_WIDTH(ENET_USER_W),.TKEEP(0))
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v2e2(eth_rx.clk,eth_rx.rst);
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// tUser = {*not used*}
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AxiStreamIf #(.DATA_WIDTH(ENET_W),.USER_WIDTH(ENET_USER_W),.TKEEP(0))
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v2e3(eth_rx.clk,eth_rx.rst);
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chdr_xport_adapter #(
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.PREAMBLE_BYTES (PREAMBLE_BYTES),
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.MAX_PACKET_BYTES (MAX_PACKET_BYTES),
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.PROTOVER (PROTOVER),
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.TBL_SIZE (RT_TBL_SIZE),
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.NODE_INST (NODE_INST),
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.ALLOW_DISC (1),
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.NET_CHDR_W (NET_CHDR_W)
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) xport_adapter_gen_i (
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.device_id (device_id),
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.my_mac (my_mac),
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.my_ip (my_ip),
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.my_udp_chdr_port (my_udp_chdr_port),
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.eth_rx (e2v2), // from Ethernet
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.e2v (e2v3), // to CHDR
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// Optional loop from Ethernet to Ethernet to talk to node
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.v2e (v2e), // from CHDR
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.eth_tx (v2e1D) // to Ethernet
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);
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if (DEBUG) begin
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`AXI4S_DEBUG_ASSIGN(v2e1,v2e1D)
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end else begin
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always_comb begin : v2e_nodebug_assign
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`AXI4S_ASSIGN(v2e1,v2e1D)
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end
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end
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// Convert incoming CHDR_W
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if (ENET_W != CHDR_W || !SYNC) begin : gen_v2e_width_conv
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axi4s_width_conv #(.SYNC_CLKS(0),.I_USER_TRAILING_BYTES(1),.O_USER_TRAILING_BYTES(1))
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v2e_width_conv (.i(v2e1), .o(v2e2));
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end else begin : gen_v2e_width_match
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always_comb begin : v2e1_assign
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`AXI4S_ASSIGN(v2e2,v2e1)
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end
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end
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// Adding so packet will be contiguous going out
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// The MAC needs bandwidth feeding it to be greater than the line rate
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if (ENET_W > CHDR_W || !SYNC) begin : gen_v2e_packet_gate
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axi4s_packet_gate #(.SIZE(17-$clog2(ENET_W)), .USE_AS_BUFF(0))
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v2e_gate_i (.clear(1'b0),.error(1'b0),.i(v2e2),.o(v2e3));
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end else begin : gen_v2e_no_packet_gate
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always_comb begin : v2e1_assign
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`AXI4S_ASSIGN(v2e3,v2e2)
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end
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end
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//---------------------------------------
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// E2V Output Buffering
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//---------------------------------------
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if (DEBUG) begin
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`AXI4S_DEBUG_ASSIGN(e2v,e2v3)
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end else begin
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always_comb begin : e2v_direct_assign
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`AXI4S_ASSIGN(e2v,e2v3)
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end
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end
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//---------------------------------------
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// C2E Path
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//---------------------------------------
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// tUser = {1'b0,trailing bytes}
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AxiStreamIf #(.DATA_WIDTH(c2e.DATA_WIDTH),.USER_WIDTH(c2e.USER_WIDTH),
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.TKEEP(c2e.TKEEP),.TUSER(c2e.TUSER))
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c2eD(c2e.clk,c2e.rst);
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// tUser = {1'b0,trailing bytes}
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AxiStreamIf #(.DATA_WIDTH(ENET_W),.USER_WIDTH(ENET_USER_W),.TKEEP(0),.MAX_PACKET_BYTES(MAX_PACKET_BYTES)) c2e1(eth_rx.clk,eth_rx.rst);
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// tUser = {1'b0,trailing bytes}
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AxiStreamIf #(.DATA_WIDTH(ENET_W),.USER_WIDTH(ENET_USER_W),.TKEEP(0),.MAX_PACKET_BYTES(MAX_PACKET_BYTES)) c2e2(eth_rx.clk,eth_rx.rst);
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// tUser = {1'b0,trailing bytes}
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AxiStreamPacketIf #(.DATA_WIDTH(ENET_W),.USER_WIDTH(ENET_USER_W),.TKEEP(0),.MAX_PACKET_BYTES(MAX_PACKET_BYTES)) c2e3(eth_rx.clk,eth_rx.rst);
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if (DEBUG) begin
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`AXI4S_DEBUG_ASSIGN(c2eD,c2e)
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end else begin
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always_comb begin : c2e_nodebug_assign
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`AXI4S_ASSIGN(c2eD,c2e)
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end
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end
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if (ENET_W != CPU_W || !SYNC) begin : gen_c2e_width_conv
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AxiStreamIf #(.DATA_WIDTH(ENET_W),.USER_WIDTH(ENET_USER_W),.TKEEP(0)) c2e1_0(eth_rx.clk,eth_rx.rst);
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axi4s_width_conv #(.I_USER_TRAILING_BYTES(c2eD.TUSER),.O_USER_TRAILING_BYTES(1),.SYNC_CLKS(0))
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c2e_width_conv (.i(c2eD), .o(c2e1_0));
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if (ENET_W > CPU_W || !SYNC) begin : gen_c2e_packet_gate
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// Adding so packet will be contiguous going out
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// I think the MAC needs bandwidth feeding it to
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// be greater than the line rate
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axi4s_packet_gate #(.SIZE(17-$clog2(ENET_W)), .USE_AS_BUFF(0))
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c2e_gate_i (.clear(1'b0),.error(1'b0),.i(c2e1_0),.o(c2e1));
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end else begin : gen_c2e_no_packet_gate
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always_comb begin : c2e1_assign
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`AXI4S_ASSIGN(c2e1,c2e1_0)
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end
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end
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end else begin : gen_c2e_width_match
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always_comb begin : c2e1_assign
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`AXI4S_ASSIGN(c2e1,c2eD)
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end
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end
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if (PREAMBLE_BYTES > 0) begin : gen_add_preamble
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// Add pad of PREAMBLE_BYTES empty bytes to the ethernet packet going
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// from the CPU to the SFP. This padding added before MAC addresses
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// aligns the source and destination IP addresses, UDP headers etc.
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// Note that the xge_mac_wrapper strips this padding to recreate the
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// ethernet packet.
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axi4s_add_bytes #(.ADD_START(0),.ADD_BYTES(PREAMBLE_BYTES)
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) add_header (
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.i(c2e1), .o(c2e2)
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);
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end else begin : gen_no_preamble
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always_comb begin : c2e2_assign
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`AXI4S_ASSIGN(c2e2,c2e1)
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end
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end
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localparam FORCE_MIN_PACKET = 1;
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if (FORCE_MIN_PACKET) begin : gen_force_min
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// add extra zero bytes to the end of a packet if it is less
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// than the minimum packet size.
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typedef enum logic {
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ST_IDLE,
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ST_AFTER
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} pad_state_t;
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pad_state_t pad_state = ST_IDLE;
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logic clk_before_minpacket;
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logic pad_last;
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always_comb clk_before_minpacket = c2e3.reached_packet_byte(MIN_PACKET_SIZE_BYTE);
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always_ff @(posedge eth_rx.clk) begin : pad_state_ff
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if (eth_rx.rst) begin
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pad_state <= ST_IDLE;
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pad_last <= 0;
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end else begin
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if (c2e3.tready && c2e3.tvalid && c2e3.tlast) begin
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pad_state <= ST_IDLE;
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end else if (c2e3.tready && c2e3.tvalid && clk_before_minpacket) begin
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pad_state <= ST_AFTER;
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end
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if (c2e3.tready && c2e3.tvalid && c2e3.tlast) begin
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pad_last <= 0;
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end else if (c2e3.tready && c2e3.tvalid && c2e2.tlast) begin
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pad_last <= 1;
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end
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end
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end
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always_comb begin : c2e3_pad
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if (pad_state == ST_IDLE) begin
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// force to a full word
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// preserve SOF if it's there, but force
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// trailing bytes to zero (full word)
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c2e3.tuser = 0;
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c2e3.tuser[ENET_USER_W-1] = c2e2.tuser[ENET_USER_W-1];
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c2e3.tvalid = c2e2.tvalid;
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// force any tdata bytes that we pad with zero
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// SW recommended forcing the padding bytes to zero
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// but I suspect we could save logic by just allowing
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// trash data.
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foreach (c2e2.tkeep[i]) begin
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if (pad_last || (i >= c2e2.tuser[ENET_USER_W-2:0] &&
|
|
c2e2.tuser[ENET_USER_W-2:0] != 0)) begin
|
|
c2e3.tdata[i*8 +:8] = 0;
|
|
end else begin
|
|
c2e3.tdata[i*8 +:8] = c2e2.tdata[i*8 +:8];
|
|
end
|
|
end
|
|
|
|
if (ENET_W < 512) begin
|
|
// hold off input if we reach the end early
|
|
if (c2e2.tlast) begin
|
|
c2e2.tready = clk_before_minpacket && c2e3.tready;
|
|
end else begin
|
|
c2e2.tready = c2e3.tready;
|
|
end
|
|
// add tlast at end of idle
|
|
c2e3.tlast = clk_before_minpacket && c2e2.tlast;
|
|
end else begin
|
|
c2e2.tready = c2e3.tready;
|
|
c2e3.tlast = c2e2.tlast;
|
|
end
|
|
|
|
end else begin
|
|
`AXI4S_ASSIGN(c2e3,c2e2)
|
|
end
|
|
|
|
end
|
|
end else begin : gen_no_force_min
|
|
always_comb begin : c2e3_assign
|
|
`AXI4S_ASSIGN(c2e3,c2e2)
|
|
end
|
|
end
|
|
|
|
|
|
//---------------------------------------
|
|
// V2E and C2E MUX
|
|
//---------------------------------------
|
|
// tUser = {1'b0,trailing bytes}
|
|
AxiStreamIf #(.DATA_WIDTH(ENET_W),.USER_WIDTH(ENET_USER_W),.TKEEP(0)) eth_tx1 (eth_rx.clk,eth_rx.rst);
|
|
// tUser = {1'b0,trailing bytes}
|
|
AxiStreamIf #(.DATA_WIDTH(ENET_W),.USER_WIDTH(ENET_USER_W)) eth_tx2 (eth_rx.clk,eth_rx.rst);
|
|
|
|
|
|
logic c2e3_tready;
|
|
always_comb begin
|
|
c2e3.tready = c2e3_tready;
|
|
end
|
|
axi_mux #(
|
|
.SIZE(2), .PRIO(0), .WIDTH(ENET_W+ENET_USER_W), .PRE_FIFO_SIZE(0), .POST_FIFO_SIZE(1)
|
|
) eth_mux_i (
|
|
.clk(eth_rx.clk), .reset(eth_rx.rst), .clear(1'b0),
|
|
.i_tdata({c2e3.tuser, c2e3.tdata, v2e3.tuser, v2e3.tdata}), .i_tlast({c2e3.tlast, v2e3.tlast}),
|
|
.i_tvalid({c2e3.tvalid, v2e3.tvalid}), .i_tready({c2e3_tready, v2e3.tready}),
|
|
.o_tdata({eth_tx1.tuser, eth_tx1.tdata}), .o_tlast(eth_tx1.tlast),
|
|
.o_tvalid(eth_tx1.tvalid), .o_tready(eth_tx1.tready)
|
|
);
|
|
|
|
|
|
|
|
// Clean up the noisy mux output. I suspect it is annoying
|
|
// the Xilinx cores that tlast and tuser(tkeep) flop around
|
|
// when tvalid isn't true.
|
|
always_comb begin : eth_tx_assign
|
|
if (eth_tx1.tvalid) begin
|
|
eth_tx2.tvalid = 1'b1;
|
|
eth_tx2.tdata = eth_tx1.tdata;
|
|
eth_tx2.tlast = eth_tx1.tlast;
|
|
// driving both tuser and tkeep
|
|
if (eth_tx1.tlast) begin
|
|
eth_tx2.tuser = eth_tx1.tuser;
|
|
eth_tx2.tkeep = eth_tx1.trailing2keep(eth_tx1.tuser);
|
|
end else begin
|
|
eth_tx2.tuser = '0;
|
|
eth_tx2.tkeep = '1;
|
|
end
|
|
end else begin
|
|
eth_tx2.tvalid = 1'b0;
|
|
eth_tx2.tdata = 'X; // use X so synth will optimize
|
|
eth_tx2.tlast = 0;
|
|
eth_tx2.tuser = '0;
|
|
eth_tx2.tkeep = '1;
|
|
end
|
|
eth_tx1.tready = eth_tx2.tready;
|
|
end
|
|
|
|
//---------------------------------------
|
|
// Output pipeline stage
|
|
//---------------------------------------
|
|
axi4s_fifo #(
|
|
.SIZE(1)
|
|
) in_reg_i (
|
|
.clear(1'b0),.space(),.occupied(),
|
|
.i(eth_tx2), .o(eth_tx)
|
|
);
|
|
|
|
|
|
endmodule // eth_ipv4_chdr_adapter
|