Martin Braun
76f67bbb0c
- This provides a CtrlPort access to reading back the device DNA - Available for US+ devices (i.e., RFSoC) and 7-series. Original-commit: 43856f90da01cebc1e4b327f4435966ccd1df602
118 lines
3.0 KiB
Verilog
118 lines
3.0 KiB
Verilog
//
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// Copyright 2023 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: device_dna
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//
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// Description:
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//
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// Read back the PL DNA.
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// When reset, this module will shift the PL DNA into an output register.
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//
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// Parameters:
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//
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// DNA_WIDTH: The width of the DNA register. UltraScale(+) devices have a 96-bit
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// DNA, 7-series have a 57-bit DNA. If DNA_WIDTH is smaller than
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// that, only LSBs will be output. If it's larger, then the DNA
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// will be zero-padded.
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// DEVICE_TYPE: Either ULTRASCALE or 7SERIES.
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//
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// Signals:
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//
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// dna: This register will hold the full DNA value.
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// valid: This is low while the DNA value register is being populated. Only
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// when high is the value in `dna' valid.
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//
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`default_nettype none
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module device_dna #(
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// Number of bits of DNA to output
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parameter DNA_WIDTH = 96,
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// For future use: Different FPGA types have different primitives for reading DNA
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parameter DEVICE_TYPE = "ULTRASCALE"
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)(
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input wire clk,
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input wire rst,
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// The device DNA
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output reg [DNA_WIDTH-1:0] dna,
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// This output is low while the dna register is being populated
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output wire valid
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);
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localparam ST_RESET = 2'd0;
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localparam ST_READ = 2'd1;
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localparam ST_SHIFT = 2'd2;
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localparam ST_DONE = 2'd3;
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localparam MAX_SHIFT = (DEVICE_TYPE == "7SERIES") ? 57 : DNA_WIDTH;
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reg [1:0] state = ST_RESET;
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reg [$clog2(DNA_WIDTH)-1:0] bit_cnt = 0;
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wire read;
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wire shift;
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wire dout0;
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always @(posedge clk) begin
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if (rst) begin
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dna <= {DNA_WIDTH{1'b0}};
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state <= ST_READ;
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end else if (state == ST_READ) begin
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state <= ST_SHIFT;
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bit_cnt <= MAX_SHIFT-1;
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end else if (state == ST_SHIFT) begin
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// Ultrascale shifts the DNA out LSB first, 7-series shifts the DNA out
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// MSB first (cf. UG-470 and UG-570 for 7-series and Ultrascale).
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if (DEVICE_TYPE == "ULTRASCALE") begin
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dna <= { dout0, dna[DNA_WIDTH-1:1] };
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end else if (DEVICE_TYPE == "7SERIES") begin
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dna <= { dna[DNA_WIDTH-2:0], dout0 };
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end
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state <= (bit_cnt == 0) ? ST_DONE : ST_SHIFT;
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bit_cnt <= bit_cnt - 1;
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end else begin
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// Nothing in ST_DONE
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end
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end
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assign read = state == ST_READ;
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assign shift = state == ST_SHIFT;
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assign valid = state == ST_DONE;
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if (DEVICE_TYPE == "ULTRASCALE") begin : gen_ultrascale_dna
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DNA_PORTE2 #(
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.SIM_DNA_VALUE(96'h12F1110_C0D111A0_11C0FFEE)
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) dna_inst (
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.CLK (clk),
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.DIN (1'b0),
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.READ (read),
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.SHIFT(shift),
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.DOUT (dout0)
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);
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end else if (DEVICE_TYPE == "7SERIES") begin : gen_7series_dna
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DNA_PORT #(
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.SIM_DNA_VALUE(57'h0D111A0_C0DE00FF)
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) dna_inst (
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.CLK (clk),
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.DIN (1'b0),
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.READ (read),
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.SHIFT(shift),
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.DOUT (dout0)
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);
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end else begin : gen_assert
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ERROR_invalid_device_type();
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end
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endmodule
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`default_nettype wire
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