Wade Fife
ea58284d4d
- Split SG1 and SG3 IP targets - Remove non-existent "RFNOC" targets Original-commit: 8320adbc18455a360d4bd26798d1f435701172b9
113 lines
3.9 KiB
Makefile
113 lines
3.9 KiB
Makefile
#
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# Copyright 2018 Ettus Research LLC
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#
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# NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target
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##-------------------
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##USRP E3XX FPGA Help
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##-------------------
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##Usage:
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## make <Targets> <Options>
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##
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##Output:
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## build/usrp_<product>_fpga_<image_type>.bit: Configuration bitstream with header
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## build/usrp_<product>_fpga_<image_type>.dts: Device tree source file
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## build/usrp_<product>_fpga_<image_type>.rpt: Build report (includes utilization and timing summary)
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# Set build option (check RTL, run synthesis, or do a full build)
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ifndef TARGET
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ifdef CHECK
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TARGET = rtl
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else ifdef SYNTH
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TARGET = synth
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else
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TARGET = bin
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endif
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endif
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TOP ?= e31x
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DEFAULT_IMAGE_CORE_FILE_E31X=e310_rfnoc_image_core.v
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DEFAULT_EDGE_FILE_E31X=$(abspath e310_static_router.hex)
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# vivado_build($1=Device, $2=Definitions)
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vivado_build = make -f Makefile.e31x.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_E31X) DEFAULT_EDGE_FILE=$(DEFAULT_EDGE_FILE_E31X)
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vivado_ip = make -f Makefile.e31x.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_E31X) DEFAULT_EDGE_FILE=$(DEFAULT_EDGE_FILE_E31X)
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# post_build($1=Device, $2=Option)
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ifeq ($(TARGET),bin)
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post_build = @\
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mkdir -p build; \
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echo "Exporting bitstream file..."; \
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cp build-$(1)/e31x.bit build/usrp_`echo $(2) | tr A-Z a-z`_fpga.bit; \
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echo "Exporting build report..."; \
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cp build-$(1)/build.rpt build/usrp_`echo $(2) | tr A-Z a-z`_fpga.rpt; \
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echo "Build DONE ... $(1)";
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else
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post_build = @echo "Skipping bitfile export."
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endif
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##
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##Supported Targets
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##-----------------
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all: E310_SG1_IDLE E310_SG3_IDLE E310_SG1 E310_SG3 ##(Default target)
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##E310_SG1_IP: Build IP for E310_SG1 only.
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E310_SG1_IP:
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+$(call vivado_ip,E310_SG1,E310_SG1=1)
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##E310_SG3_IP: Build IP for E310_SG3 only.
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E310_SG3_IP:
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+$(call vivado_ip,E310_SG3,E310_SG3=1)
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##E310_SG1_IDLE: Build USRP E3XX idle design (Speed Grade 1).
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E310_SG1_IDLE E3XX_idle: E310_SG1_IP build/usrp_e310_sg1_idle_fpga.dts
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$(call vivado_build,E310_SG1, E310_IDLE_IMAGE=1 E310_SG1=1)
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$(call post_build,$@,E310_SG1_IDLE)
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##E310_SG3_IDLE: Build USRP E3XX idle design (Speed Grade 3).
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E310_SG3_IDLE E3XX_idle_sg3: E310_SG3_IP build/usrp_e310_sg3_idle_fpga.dts
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$(call vivado_build,E310_SG3, E310_IDLE_IMAGE=1 E310_SG3=1)
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$(call post_build,$@,E310_SG3_IDLE)
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##E310_SG1: Build USRP E3XX (Speed Grade 1).
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E310_SG1 E310: E310_SG1_IP build/usrp_e310_sg1_fpga.dts
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$(call vivado_build,E310_SG1, E310_SG1=1 $(if $(DRAM),ENABLE_DRAM=1,))
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$(call post_build,$@,E310_SG1)
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##E310_SG3: Build USRP E3XX (Speed Grade 3).
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E310_SG3 E310_sg3: E310_SG3_IP build/usrp_e310_sg3_fpga.dts
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$(call vivado_build,E310_SG3, E310_SG3=1 $(if $(DRAM),ENABLE_DRAM=1,))
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$(call post_build,$@,E310_SG3)
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build/%.dts: dts/%.dts dts/*.dtsi
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-mkdir -p build
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${CC} -o $@ -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ $<
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clean: ##Clean up all target build outputs.
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@echo "Cleaning targets..."
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@rm -rf build-E3*
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@rm -rf build
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cleanall: ##Clean up all target and ip build outputs.
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@echo "Cleaning targets and IP..."
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@rm -rf build-ip
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@rm -rf build-E3*
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@rm -rf build
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help: ##Show this help message.
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@grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//'
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##
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##Supported Options
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##-----------------
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##DRAM=1 Include DDR3 SDRAM memory controller IP in the FPGA build.
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## Note: The RFNoC image core must also be configured to use DRAM.
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##GUI=1 Launch the build in the Vivado GUI.
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##CHECK=1 Launch the syntax checker instead of building a bitfile.
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##SYNTH=1 Launch the build but stop after synthesis.
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##TOP=<module> Specify a top module for syntax checking. (Optional. Default is the bitfile top)
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.PHONY: all clean cleanall help
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