Wade Fife
5f4d53eacb
- Fix NODE_INST - Fix RFNOC_PROTOVER - Add option to use SystemVerilog transport adapter for raw UDP Original-commit: 0114e108af63d9ac785649c8099a042299624943
655 lines
23 KiB
Verilog
655 lines
23 KiB
Verilog
///////////////////////////////////////////////////////////////////
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//
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// Copyright 2018 Ettus Research, A National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0
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//
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// Module: e320_mgt_io_core
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// Description:
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// Encapsulates the PSC/PMA, the MAC layer and the control interface
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// for 1GbE, 10GbE and Aurora
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//
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//////////////////////////////////////////////////////////////////////
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module e320_mgt_io_core #(
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parameter PROTOCOL = "10GbE", // Must be {10GbE, 1GbE, Aurora, Disabled}
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parameter [13:0] REG_BASE = 14'h0,
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parameter REG_DWIDTH = 32,
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parameter REG_AWIDTH = 14,
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parameter [7:0] PORTNUM = 8'd0,
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parameter MDIO_EN = 0,
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parameter [4:0] MDIO_PHYADDR = 5'd0
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)(
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// Resets
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input areset,
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input bus_rst,
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// Clocks
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input gt_refclk,
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input gb_refclk,
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input misc_clk,
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input bus_clk,
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// SFP high-speed IO
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output txp,
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output txn,
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input rxp,
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input rxn,
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// SFP low-speed IO
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input sfpp_rxlos,
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input sfpp_tx_fault,
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output sfpp_tx_disable,
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// Data port: Ethernet TX
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input [63:0] s_axis_tdata,
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input [3:0] s_axis_tuser,
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input s_axis_tlast,
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input s_axis_tvalid,
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output s_axis_tready,
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// Data port: Ethernet RX
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output [63:0] m_axis_tdata,
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output [3:0] m_axis_tuser,
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output m_axis_tlast,
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output m_axis_tvalid,
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input m_axis_tready,
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// Register port
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input reg_wr_req,
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input [REG_AWIDTH-1:0] reg_wr_addr,
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input [REG_DWIDTH-1:0] reg_wr_data,
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input reg_rd_req,
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input [REG_AWIDTH-1:0] reg_rd_addr,
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output reg_rd_resp,
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output [REG_DWIDTH-1:0] reg_rd_data,
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// Misc
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output [31:0] port_info,
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output link_up,
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output reg activity
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);
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//-----------------------------------------------------------------
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// Registers
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//-----------------------------------------------------------------
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localparam [7:0] COMPAT_NUM = 8'd2;
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// Common registers
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localparam REG_PORT_INFO = REG_BASE + 'h0;
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localparam REG_MAC_CTRL_STATUS = REG_BASE + 'h4;
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localparam REG_PHY_CTRL_STATUS = REG_BASE + 'h8;
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localparam REG_MAC_LED_CTL = REG_BASE + 'hC;
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// Ethernet specific
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localparam REG_ETH_MDIO_BASE = REG_BASE + 'h10;
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// Aurora specific
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localparam REG_AURORA_OVERRUNS = REG_BASE + 'h20;
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localparam REG_CHECKSUM_ERRORS = REG_BASE + 'h24;
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localparam REG_BIST_CHECKER_SAMPS = REG_BASE + 'h28;
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localparam REG_BIST_CHECKER_ERRORS = REG_BASE + 'h2C;
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wire reg_rd_resp_mdio;
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reg reg_rd_resp_glob = 1'b0;
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wire [REG_DWIDTH-1:0] reg_rd_data_mdio;
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reg [REG_DWIDTH-1:0] reg_rd_data_glob = 32'h0;
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// Protocol specific constants
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wire [7:0] mgt_protocol;
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wire [31:0] mac_ctrl_rst_val, phy_ctrl_rst_val;
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wire [1:0] mac_led_ctl_rst_val = 2'h0;
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// Flush logic: If the link is not up, we will flush all packets coming from
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// the device. This avoids the MAC backpressuring when the PHY is down.
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// The device will always send discovery packets to the transports during
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// initialization, and they have no way of knowing if it's safe to travel
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// down this route. c2mac == "CHDR to MAC"
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wire [63:0] c2mac_tdata;
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wire [3:0] c2mac_tuser;
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wire c2mac_tlast;
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wire c2mac_tvalid;
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wire c2mac_tready;
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axis_packet_flush #(
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.WIDTH(64+3), // tdata + tuser
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.TIMEOUT_W(1), // Not using timeout
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.FLUSH_PARTIAL_PKTS(0),
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.PIPELINE("NONE")
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) linkup_flush (
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.clk(bus_clk),
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.reset(bus_rst),
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.enable(~link_up), // enable flushing when link down
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.timeout(1'b0),
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.flushing(/* not required */),
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.done(/* not required */),
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// Input from device/crossbar
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.s_axis_tdata ({s_axis_tuser, s_axis_tdata}),
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.s_axis_tlast (s_axis_tlast),
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.s_axis_tvalid (s_axis_tvalid),
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.s_axis_tready (s_axis_tready),
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// Output to MAC
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.m_axis_tdata ({c2mac_tuser, c2mac_tdata}),
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.m_axis_tlast (c2mac_tlast),
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.m_axis_tvalid (c2mac_tvalid),
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.m_axis_tready (c2mac_tready)
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);
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generate
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if (PROTOCOL == "Aurora") begin
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assign mgt_protocol = 8'd3;
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assign mac_ctrl_rst_val = 32'h0;
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assign phy_ctrl_rst_val = 32'h0;
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end else if (PROTOCOL == "10GbE") begin
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assign mgt_protocol = 8'd2;
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assign mac_ctrl_rst_val = {31'h0, 1'b1}; // tx_enable on reset
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assign phy_ctrl_rst_val = 32'h0;
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end else if (PROTOCOL == "1GbE") begin
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assign mgt_protocol = 8'd1;
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assign mac_ctrl_rst_val = {31'h0, 1'b1}; // tx_enable on reset
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assign phy_ctrl_rst_val = 32'h0;
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end else begin
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assign mgt_protocol = 8'd0;
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assign mac_ctrl_rst_val = 32'h0;
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assign phy_ctrl_rst_val = 32'h0;
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end
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endgenerate
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// Writable registers
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reg [31:0] mac_ctrl_reg = 32'h0;
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reg [31:0] phy_ctrl_reg = 32'h0;
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reg [1:0] mac_led_ctl = 2'h0;
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always @(posedge bus_clk) begin
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if (bus_rst) begin
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mac_ctrl_reg <= mac_ctrl_rst_val;
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phy_ctrl_reg <= phy_ctrl_rst_val;
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mac_led_ctl <= mac_led_ctl_rst_val;
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end else if (reg_wr_req) begin
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case(reg_wr_addr)
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REG_MAC_CTRL_STATUS:
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mac_ctrl_reg <= reg_wr_data;
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REG_PHY_CTRL_STATUS:
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phy_ctrl_reg <= reg_wr_data;
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REG_MAC_LED_CTL:
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mac_led_ctl <= reg_wr_data[1:0];
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endcase
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end
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end
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// Readable registers
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wire [31:0] overruns;
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wire [31:0] checksum_errors;
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wire [47:0] bist_checker_samps;
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wire [47:0] bist_checker_errors;
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wire [31:0] mac_status, phy_status;
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wire [31:0] mac_status_bclk, phy_status_bclk;
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assign port_info = {COMPAT_NUM, 6'h0, activity, link_up, mgt_protocol, PORTNUM};
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always @(posedge bus_clk) begin
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// No reset handling needed for readback
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if (reg_rd_req) begin
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reg_rd_resp_glob <= 1'b1;
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case(reg_rd_addr)
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REG_PORT_INFO:
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reg_rd_data_glob <= port_info;
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REG_MAC_CTRL_STATUS:
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reg_rd_data_glob <= mac_status_bclk;
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REG_PHY_CTRL_STATUS:
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reg_rd_data_glob <= phy_status_bclk;
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REG_MAC_LED_CTL:
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reg_rd_data_glob <= {30'd0, mac_led_ctl};
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REG_AURORA_OVERRUNS:
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reg_rd_data_glob <= overruns;
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REG_CHECKSUM_ERRORS:
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reg_rd_data_glob <= checksum_errors;
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REG_BIST_CHECKER_SAMPS:
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reg_rd_data_glob <= bist_checker_samps[47:16]; //Scale num samples by 2^16
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REG_BIST_CHECKER_ERRORS:
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reg_rd_data_glob <= bist_checker_errors[31:0]; //Don't scale errors
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default:
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reg_rd_resp_glob <= 1'b0;
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endcase
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end if (reg_rd_resp_glob) begin
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reg_rd_resp_glob <= 1'b0;
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end
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end
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synchronizer #( .STAGES(2), .WIDTH(32), .INITIAL_VAL(32'h0) ) mac_status_sync_i (
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.clk(bus_clk), .rst(1'b0), .in(mac_status), .out(mac_status_bclk)
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);
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synchronizer #( .STAGES(2), .WIDTH(32), .INITIAL_VAL(32'h0) ) phy_status_sync_i (
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.clk(bus_clk), .rst(1'b0), .in(phy_status), .out(phy_status_bclk)
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);
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// Regport Mux for response
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regport_resp_mux #(
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.WIDTH (REG_DWIDTH),
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.NUM_SLAVES (2)
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) reg_resp_mux_i (
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.clk(bus_clk), .reset(bus_rst),
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.sla_rd_resp({reg_rd_resp_mdio, reg_rd_resp_glob}),
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.sla_rd_data({reg_rd_data_mdio, reg_rd_data_glob}),
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.mst_rd_resp(reg_rd_resp), .mst_rd_data(reg_rd_data)
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);
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//-----------------------------------------------------------------
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// Ethernet Specific: MDIO
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//-----------------------------------------------------------------
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wire mdc, mdio_m2s, mdio_s2m, mdio_s2m_sync;
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generate
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if ((PROTOCOL == "10GbE" || PROTOCOL == "1GbE") && (MDIO_EN == 1)) begin
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mdio_master #(
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.REG_BASE (REG_ETH_MDIO_BASE),
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.REG_AWIDTH (REG_AWIDTH),
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.MDC_DIVIDER (8'd200)
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) mdio_master_i (
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.clk (bus_clk),
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.rst (bus_rst),
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.mdc (mdc),
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.mdio_in (mdio_s2m_sync),
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.mdio_out (mdio_m2s),
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.mdio_tri (),
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.reg_wr_req (reg_wr_req),
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.reg_wr_addr (reg_wr_addr),
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.reg_wr_data (reg_wr_data),
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.reg_rd_req (reg_rd_req),
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.reg_rd_addr (reg_rd_addr),
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.reg_rd_data (reg_rd_data_mdio),
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.reg_rd_resp (reg_rd_resp_mdio)
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);
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// We can cross mdio_s2m into the bus_clk domain. A synchronizer is safe
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// here because the bit is inherently async
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synchronizer #(.INITIAL_VAL(1'b0)) mdio_s2m_sync_i (
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.clk(bus_clk), .rst(1'b0 /* no reset */), .in(mdio_s2m), .out(mdio_s2m_sync)
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);
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end else begin
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assign mdc = 1'b0;
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assign mdio_m2s = 1'b0;
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assign reg_rd_resp_mdio = 1'b0;
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assign reg_rd_data_mdio = 32'h0;
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end
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endgenerate
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generate
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if (PROTOCOL == "10GbE") begin
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//-----------------------------------------------------------------
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// 10 Gigabit Ethernet
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//-----------------------------------------------------------------
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wire [63:0] xgmii_txd;
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wire [7:0] xgmii_txc;
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wire [63:0] xgmii_rxd;
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wire [7:0] xgmii_rxc;
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wire xge_phy_resetdone;
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ten_gige_phy ten_gige_phy_i
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(
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// Clocks and Reset
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.areset(areset | phy_ctrl_reg[0]), // Asynchronous reset for entire core.
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.refclk(gt_refclk), // Transciever reference clock: 156.25MHz
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.clk156(gb_refclk), // Globally buffered core clock: 156.25MHz
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.dclk(misc_clk), // Management/DRP clock: 78.125MHz
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.sim_speedup_control(1'b0),
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// GMII Interface (client MAC <=> PCS)
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.xgmii_txd(xgmii_txd), // Transmit data from client MAC.
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.xgmii_txc(xgmii_txc), // Transmit control signal from client MAC.
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.xgmii_rxd(xgmii_rxd), // Received Data to client MAC.
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.xgmii_rxc(xgmii_rxc), // Received control signal to client MAC.
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// Tranceiver Interface
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.txp(txp), // Differential +ve of serial transmission from PMA to PMD.
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.txn(txn), // Differential -ve of serial transmission from PMA to PMD.
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.rxp(rxp), // Differential +ve for serial reception from PMD to PMA.
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.rxn(rxn), // Differential -ve for serial reception from PMD to PMA.
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// Management: MDIO Interface
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.mdc(mdc), // Management Data Clock
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.mdio_in(mdio_m2s), // Management Data In
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.mdio_out(mdio_s2m), // Management Data Out
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.mdio_tri(), // Management Data Tristate
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.prtad(MDIO_PHYADDR), // MDIO address
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// General IO's
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.core_status(phy_status[7:0]), // Core status
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.resetdone(xge_phy_resetdone),
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.signal_detect(~sfpp_rxlos), // Input from PMD to indicate presence of optical input. (Undocumented, but it seems Xilinx expect this to be inverted.)
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.tx_fault(sfpp_tx_fault),
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.tx_disable(sfpp_tx_disable)
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);
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xge_mac_wrapper #(
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.PORTNUM(PORTNUM),
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.WISHBONE(0)
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) xge_mac_wrapper_i (
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// XGMII
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.xgmii_clk(gb_refclk),
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.xgmii_txd(xgmii_txd),
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.xgmii_txc(xgmii_txc),
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.xgmii_rxd(xgmii_rxd),
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.xgmii_rxc(xgmii_rxc),
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// Client FIFO Interfaces
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.sys_clk(bus_clk),
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.sys_rst(bus_rst),
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.rx_tdata(m_axis_tdata),
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.rx_tuser(m_axis_tuser),
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.rx_tlast(m_axis_tlast),
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.rx_tvalid(m_axis_tvalid),
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.rx_tready(m_axis_tready),
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.tx_tdata(c2mac_tdata),
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.tx_tuser(c2mac_tuser), // Bit[3] (error) is ignored for now.
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.tx_tlast(c2mac_tlast),
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.tx_tvalid(c2mac_tvalid),
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.tx_tready(c2mac_tready),
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// Other
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.phy_ready(xge_phy_resetdone),
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.ctrl_tx_enable(mac_ctrl_reg[0]),
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.status_crc_error(mac_status[0]),
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.status_fragment_error(mac_status[1]),
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.status_txdfifo_ovflow(mac_status[2]),
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.status_txdfifo_udflow(mac_status[3]),
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.status_rxdfifo_ovflow(mac_status[4]),
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.status_rxdfifo_udflow(mac_status[5]),
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.status_pause_frame_rx(mac_status[6]),
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.status_local_fault(mac_status[7]),
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.status_remote_fault(mac_status[8]),
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.wb_ack_o(),
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.wb_dat_o(),
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.wb_adr_i(1'b0),
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.wb_clk_i(1'b0),
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.wb_cyc_i(1'b0),
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.wb_dat_i(1'b0),
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.wb_rst_i(1'b0),
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.wb_stb_i(1'b0),
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.wb_we_i (1'b0),
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.wb_int_o()
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);
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assign phy_status[31:8] = 24'h0;
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assign mac_status[31:9] = 23'h0;
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assign link_up = phy_status_bclk[0];
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end else if (PROTOCOL == "1GbE") begin
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//-----------------------------------------------------------------
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// 1 Gigabit Ethernet
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//-----------------------------------------------------------------
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wire [7:0] gmii_txd, gmii_rxd;
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wire gmii_tx_en, gmii_tx_er, gmii_rx_dv, gmii_rx_er;
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wire gmii_clk;
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wire gt0_qplloutclk, gt0_qplloutrefclk; //unused in 7-series Zynq
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assign gt0_qplloutclk = 1'b0;
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assign gt0_qplloutrefclk = 1'b0;
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assign sfpp_tx_disable = 1'b0; // Always on.
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one_gige_phy one_gige_phy_i
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(
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.reset(areset | phy_ctrl_reg[0]), // Asynchronous reset for entire core.
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.independent_clock(bus_clk),
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// Tranceiver Interface
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.gtrefclk(gt_refclk), // Reference clock for MGT: 125MHz, very high quality.
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.gtrefclk_bufg(gb_refclk), // Reference clock routed through a BUFG
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.txp(txp), // Differential +ve of serial transmission from PMA to PMD.
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.txn(txn), // Differential -ve of serial transmission from PMA to PMD.
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.rxp(rxp), // Differential +ve for serial reception from PMD to PMA.
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.rxn(rxn), // Differential -ve for serial reception from PMD to PMA.
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// GMII Interface (client MAC <=> PCS)
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.gmii_clk(gmii_clk), // Clock to client MAC.
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.gmii_txd(gmii_txd), // Transmit data from client MAC.
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.gmii_tx_en(gmii_tx_en), // Transmit control signal from client MAC.
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.gmii_tx_er(gmii_tx_er), // Transmit control signal from client MAC.
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.gmii_rxd(gmii_rxd), // Received Data to client MAC.
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.gmii_rx_dv(gmii_rx_dv), // Received control signal to client MAC.
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.gmii_rx_er(gmii_rx_er), // Received control signal to client MAC.
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// Management: MDIO Interface
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.mdc(mdc), // Management Data Clock
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.mdio_i(mdio_m2s), // Management Data In
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.mdio_o(mdio_s2m), // Management Data Out
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.mdio_t(), // Management Data Tristate
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.phyaddr(MDIO_PHYADDR), // MDIO address
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.configuration_vector(5'd0), // Alternative to MDIO interface.
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.configuration_valid(1'b1), // Validation signal for Config vector (MUST be 1 for proper functionality...undocumented)
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// General IO's
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.status_vector(phy_status[15:0]), // Core status.
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.signal_detect(1'b1 /*Optical module not supported*/) // Input from PMD to indicate presence of optical input.
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);
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simple_gemac_wrapper #(.RX_FLOW_CTRL(0), .PORTNUM(PORTNUM)) simple_gemac_wrapper_i
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(
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.clk125(gmii_clk),
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.reset(areset),
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.GMII_GTX_CLK(),
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.GMII_TX_EN(gmii_tx_en),
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.GMII_TX_ER(gmii_tx_er),
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.GMII_TXD(gmii_txd),
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.GMII_RX_CLK(gmii_clk),
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.GMII_RX_DV(gmii_rx_dv),
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.GMII_RX_ER(gmii_rx_er),
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.GMII_RXD(gmii_rxd),
|
|
|
|
.sys_clk(bus_clk),
|
|
.rx_tdata(m_axis_tdata),
|
|
.rx_tuser(m_axis_tuser),
|
|
.rx_tlast(m_axis_tlast),
|
|
.rx_tvalid(m_axis_tvalid),
|
|
.rx_tready(m_axis_tready),
|
|
.tx_tdata(c2mac_tdata),
|
|
.tx_tuser(c2mac_tuser),
|
|
.tx_tlast(c2mac_tlast),
|
|
.tx_tvalid(c2mac_tvalid),
|
|
.tx_tready(c2mac_tready),
|
|
|
|
.wb_clk_i(1'b0),
|
|
.wb_rst_i(1'b0),
|
|
.wb_adr_i(8'h0),
|
|
.wb_dat_i(32'h0),
|
|
.wb_we_i(1'b0),
|
|
.wb_stb_i(1'b0),
|
|
.wb_cyc_i(1'b0),
|
|
.wb_dat_o(),
|
|
.wb_ack_o(),
|
|
.wb_int_o(),
|
|
.mdc(),
|
|
.mdio_out(1'b0),
|
|
.mdio_tri(),
|
|
.mdio_in(),
|
|
.debug_tx(),
|
|
.debug_rx()
|
|
);
|
|
|
|
assign phy_status[31:16] = 16'h0;
|
|
assign mac_status[31:0] = 32'h0;
|
|
assign link_up = phy_status_bclk[0];
|
|
|
|
assign gt_tx_out_clk_unbuf = 1'b0;
|
|
|
|
end else if (PROTOCOL == "Aurora") begin
|
|
|
|
//-----------------------------------------------------------------
|
|
// Aurora
|
|
//-----------------------------------------------------------------
|
|
wire user_clk, user_rst;
|
|
wire [63:0] m2p_tdata, p2m_tdata;
|
|
wire m2p_tvalid, m2p_tready, p2m_tvalid;
|
|
wire channel_up, hard_err, soft_err, mac_crit_err;
|
|
|
|
wire bist_checker_en = mac_ctrl_reg[0];
|
|
wire bist_gen_en = mac_ctrl_reg[1];
|
|
wire bist_loopback_en = mac_ctrl_reg[2];
|
|
wire [5:0] bist_gen_rate = mac_ctrl_reg[8:3];
|
|
wire phy_areset = mac_ctrl_reg[9];
|
|
wire mac_clear = mac_ctrl_reg[10];
|
|
wire bist_checker_locked;
|
|
|
|
assign sfpp_tx_disable = 1'b0; // Always on.
|
|
|
|
aurora_phy_x1 aurora_phy_i (
|
|
// Resets
|
|
.areset(areset | phy_areset),
|
|
// Clocks
|
|
.refclk(gt_refclk),
|
|
.init_clk(misc_clk),
|
|
.user_clk(user_clk),
|
|
.user_rst(user_rst),
|
|
// GTX Serial I/O
|
|
.tx_p(txp),
|
|
.tx_n(txn),
|
|
.rx_p(rxp),
|
|
.rx_n(rxn),
|
|
// AXI4-Stream TX Interface
|
|
.s_axis_tdata(m2p_tdata),
|
|
.s_axis_tvalid(m2p_tvalid),
|
|
.s_axis_tready(m2p_tready),
|
|
// AXI4-Stream RX Interface
|
|
.m_axis_tdata(p2m_tdata),
|
|
.m_axis_tvalid(p2m_tvalid),
|
|
// AXI4-Lite Config Interface (unused)
|
|
.s_axi_awaddr(32'h0),
|
|
.s_axi_araddr(32'h0),
|
|
.s_axi_awvalid(1'b0),
|
|
.s_axi_awready(),
|
|
.s_axi_wdata(32'h0),
|
|
.s_axi_wvalid(1'b0),
|
|
.s_axi_wstrb(1'b0),
|
|
.s_axi_wready(),
|
|
.s_axi_bvalid(),
|
|
.s_axi_bresp(),
|
|
.s_axi_bready(1'b1),
|
|
.s_axi_arready(),
|
|
.s_axi_arvalid(1'b0),
|
|
.s_axi_rdata(),
|
|
.s_axi_rvalid(),
|
|
.s_axi_rresp(),
|
|
.s_axi_rready(1'b1),
|
|
// Status and Error Reporting Interface
|
|
.channel_up(channel_up),
|
|
.hard_err(hard_err),
|
|
.soft_err(soft_err)
|
|
);
|
|
|
|
aurora_axis_mac #(
|
|
.PHY_ENDIANNESS ("LITTLE"),
|
|
.PACKET_MODE (1),
|
|
.MAX_PACKET_SIZE(1024),
|
|
.BIST_ENABLED (1)
|
|
) aurora_mac_i (
|
|
// Clocks and resets
|
|
.phy_clk(user_clk), .phy_rst(user_rst),
|
|
.sys_clk(bus_clk), .sys_rst(bus_rst),
|
|
.clear(mac_clear),
|
|
// PHY Interface (Synchronous to phy_clk)
|
|
.phy_s_axis_tdata(p2m_tdata),
|
|
.phy_s_axis_tvalid(p2m_tvalid),
|
|
.phy_m_axis_tdata(m2p_tdata),
|
|
.phy_m_axis_tvalid(m2p_tvalid),
|
|
.phy_m_axis_tready(m2p_tready),
|
|
// User Interface (Synchronous to sys_clk)
|
|
.s_axis_tdata(c2mac_tdata),
|
|
.s_axis_tlast(c2mac_tlast),
|
|
.s_axis_tvalid(c2mac_tvalid),
|
|
.s_axis_tready(c2mac_tready),
|
|
.m_axis_tdata(m_axis_tdata),
|
|
.m_axis_tlast(m_axis_tlast),
|
|
.m_axis_tvalid(m_axis_tvalid),
|
|
.m_axis_tready(m_axis_tready),
|
|
// PHY Status Inputs (Synchronous to phy_clk)
|
|
.channel_up(channel_up),
|
|
.hard_err(hard_err),
|
|
.soft_err(soft_err),
|
|
// Status and Error Outputs (Synchronous to sys_clk)
|
|
.overruns(overruns),
|
|
.soft_errors(),
|
|
.checksum_errors(checksum_errors),
|
|
.critical_err(mac_crit_err),
|
|
// BIST Interface (Synchronous to sys_clk)
|
|
.bist_gen_en(bist_gen_en),
|
|
.bist_gen_rate(bist_gen_rate),
|
|
.bist_checker_en(bist_checker_en),
|
|
.bist_loopback_en(bist_loopback_en),
|
|
.bist_checker_locked(bist_checker_locked),
|
|
.bist_checker_samps(bist_checker_samps),
|
|
.bist_checker_errors(bist_checker_errors)
|
|
);
|
|
|
|
assign m_axis_tuser = 4'd0;
|
|
|
|
wire channel_up_bclk, hard_err_bclk, soft_err_bclk, mac_crit_err_bclk;
|
|
synchronizer #(.INITIAL_VAL(1'b0)) channel_up_sync (
|
|
.clk(bus_clk), .rst(1'b0 /* no reset */), .in(channel_up), .out(channel_up_bclk));
|
|
synchronizer #(.INITIAL_VAL(1'b0)) hard_err_sync (
|
|
.clk(bus_clk), .rst(1'b0 /* no reset */), .in(hard_err), .out(hard_err_bclk));
|
|
synchronizer #(.INITIAL_VAL(1'b0)) soft_err_sync (
|
|
.clk(bus_clk), .rst(1'b0 /* no reset */), .in(soft_err), .out(soft_err_bclk));
|
|
synchronizer #(.INITIAL_VAL(1'b0)) mac_crit_err_sync (
|
|
.clk(bus_clk), .rst(1'b0 /* no reset */), .in(mac_crit_err), .out(mac_crit_err_bclk));
|
|
|
|
reg [19:0] bist_lock_latency;
|
|
always @(posedge bus_clk) begin
|
|
if (!bist_checker_en && !bist_checker_locked)
|
|
bist_lock_latency <= 20'd0;
|
|
else if (bist_checker_en && !bist_checker_locked)
|
|
bist_lock_latency <= bist_lock_latency + 20'd1;
|
|
end
|
|
|
|
reg mac_crit_err_latch;
|
|
always @(posedge bus_clk) begin
|
|
if (bus_rst | mac_clear) begin
|
|
mac_crit_err_latch <= 1'b0;
|
|
end else begin
|
|
if (mac_crit_err_bclk)
|
|
mac_crit_err_latch <= 1'b1;
|
|
end
|
|
end
|
|
|
|
assign phy_status = {30'd0, hard_err, channel_up};
|
|
assign mac_status = {
|
|
6'h0, //[31:26]
|
|
mac_crit_err_latch, //[25]
|
|
1'b1, //[24]
|
|
1'b0, //[23]
|
|
1'b0, //[22]
|
|
1'b0, //[21]
|
|
1'b0, //[20]
|
|
bist_lock_latency[19:4], //[19:4]
|
|
bist_checker_locked, //[3]
|
|
soft_err_bclk, //[2]
|
|
hard_err_bclk, //[1]
|
|
channel_up_bclk //[0]
|
|
};
|
|
|
|
assign link_up = channel_up_bclk;
|
|
|
|
end else begin
|
|
|
|
//-----------------------------------------------------------------
|
|
// Disabled
|
|
//-----------------------------------------------------------------
|
|
|
|
assign phy_status = 'h0;
|
|
assign mac_status = 'h0;
|
|
assign link_up = 1'b0;
|
|
|
|
assign sfpp_tx_disable = 1'b0; // Always on.
|
|
|
|
assign c2mac_tready = 1'b1;
|
|
assign m_axis_tdata = 64'h0;
|
|
assign m_axis_tuser = 4'h0;
|
|
assign m_axis_tlast = 1'b0;
|
|
assign m_axis_tvalid = 1'b0;
|
|
|
|
end
|
|
endgenerate
|
|
|
|
wire identify_enable = mac_led_ctl[0];
|
|
wire identify_value = mac_led_ctl[1];
|
|
|
|
//-----------------------------------------------------------------
|
|
// Activity detector
|
|
//-----------------------------------------------------------------
|
|
wire activity_int;
|
|
|
|
pulse_stretch act_pulse_str_i (
|
|
.clk(bus_clk),
|
|
.rst(bus_rst | ~link_up),
|
|
.pulse((s_axis_tvalid & s_axis_tready) | (m_axis_tvalid & m_axis_tready)),
|
|
.pulse_stretched(activity_int)
|
|
);
|
|
|
|
always @ (posedge bus_clk) activity <= identify_enable ? identify_value : activity_int;
|
|
|
|
endmodule
|