Andrew Moch
8cb9bdd331
Add a SystemVerilog interface for connecting AXI4 ports, and an associated header file with helper macros. Original-commit: 04d29e85b0c0698e3de96b54fd3f6e04eb439f74
14 lines
334 B
Makefile
14 lines
334 B
Makefile
#
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# Copyright 2021 Ettus Research, A National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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##################################################
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# RFNoC Utility Sources
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##################################################
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AXI4_SV_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/axi4_sv/, \
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PkgAxi.sv \
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AxiIf.sv \
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))
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