Andrew Moch
09751b661e
This adds a simulation make target that allows you to run ModelSim natively rather than through Vivado. Adds or modifies the following simulation make targets: make vlint - Brake up compilation to Verilog/SystemVerilog/VHDL make modelsim - Depends on make vlint and invokes modelsim Adds the following variables: MODELSIM_ARGS - Added to invocation of ModelSim SVLOG_ARGS - Added to SystemVerilog invocation of vlog VLOG_ARGS - Added to Verilog invocation of vlog VHDL_ARGS - Added to VHDL invocation of vcom Original-commit: b296b26053d4437b8ae97e3df415a3d041b7b51e
167 lines
5.8 KiB
Makefile
167 lines
5.8 KiB
Makefile
#
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# Copyright 2014-2015 Ettus Research
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#
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# -------------------------------------------------------------------
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# Mode switches
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# -------------------------------------------------------------------
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# Calling with FAST:=1 will switch to using unifast libs
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ifeq ($(FAST),1)
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SIM_FAST=true
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else
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SIM_FAST=false
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endif
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# -------------------------------------------------------------------
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# Path variables
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# -------------------------------------------------------------------
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ifdef SIM_COMPLIBDIR
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COMPLIBDIR = $(call RESOLVE_PATH,$(SIM_COMPLIBDIR))
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endif
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# Parse part name from ID
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PART_NAME=$(subst /,,$(PART_ID))
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# -------------------------------------------------------------------
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# Usage: SETUP_AND_LAUNCH_SIMULATION
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# Args: $1 = Simulator Name
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# -------------------------------------------------------------------
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# Resolve path
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EXP_DESIGN_SRCS = $(call RESOLVE_PATHS,$(DESIGN_SRCS))
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EXP_SIM_SRCS = $(call RESOLVE_PATHS,$(SIM_SRCS))
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EXP_INC_SRCS = $(call RESOLVE_PATHS,$(INC_SRCS))
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# (NOQ) No quotes!
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NOQ_DESIGN_SRCS := $(subst $\",,$(EXP_DESIGN_SRCS))
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NOQ_SIM_SRCS := $(subst $\",,$(EXP_SIM_SRCS))
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NOQ_INC_SRCS := $(subst $\",,$(EXP_INC_SRCS))
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# Separate out VHDL
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NOQ_DESIGN_VHDL := $(filter %.vhd,$(NOQ_DESIGN_SRCS))
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NOQ_SIM_VHDL := $(filter %.vhd,$(NOQ_SIM_SRCS))
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NOQ_VHDL := $(NOQ_DESIGN_VHDL) $(NOQ_SIM_VHDL)
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# Separate out System Verilog
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NOQ_DESIGN_SV := $(filter %.sv,$(NOQ_DESIGN_SRCS))
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NOQ_SIM_SV := $(filter %.sv,$(NOQ_SIM_SRCS))
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NOQ_SV := $(NOQ_DESIGN_SV) $(NOQ_SIM_SV)
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# Fetch packages from include list to compile
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NOQ_PKG_SV := $(filter %.sv,$(NOQ_INC_SRCS))
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# Seperate out Verilog
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NOQ_INC_DIRS := $(sort $(dir $(NOQ_INC_SRCS)))
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NOQ_DESIGN_VERILOG := $(filter %.v,$(NOQ_DESIGN_SRCS))
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NOQ_SIM_VERILOG := $(filter %.v,$(NOQ_SIM_SRCS))
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NOQ_VERILOG := $(NOQ_DESIGN_VERILOG) $(NOQ_SIM_VERILOG)
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# Modelsim Load libraries
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MODELSIM_LIBS += unisims_ver
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# Arguments for various simulators
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MODELSIM_ARGS += -quiet
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SVLOG_ARGS += -quiet
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SVLOG_ARGS += +define+WORKING_DIR="\"${CURDIR}\""
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VLOG_ARGS += -quiet
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VLOG_ARGS += +define+WORKING_DIR="\"${CURDIR}\""
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VHDL_ARGS += -quiet
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# Working directory for standalone ModelSim execution
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MODELSIM_PROJ_DIR ?= modelsim_proj
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# Check if we want to load the ModelSim GUI
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ifeq ($(GUI), 1)
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MODELSIM_ARGS += -do "run -all"
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else
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MODELSIM_ARGS += -c -do "run -all; quit -f"
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endif
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SETUP_AND_LAUNCH_SIMULATION = \
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@ \
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export VIV_SIMULATOR=$1; \
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export VIV_DESIGN_SRCS=$(EXP_DESIGN_SRCS); \
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export VIV_SIM_SRCS=$(EXP_SIM_SRCS); \
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export VIV_INC_SRCS=$(EXP_INC_SRCS); \
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export VIV_SIM_TOP=$(SIM_TOP); \
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export VIV_SYNTH_TOP="$(SYNTH_DUT)"; \
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export VIV_PART_NAME=$(PART_NAME); \
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export VIV_SIM_RUNTIME=$(SIM_RUNTIME_US); \
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export VIV_SIM_FAST="$(SIM_FAST)"; \
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export VIV_SIM_COMPLIBDIR=$(COMPLIBDIR); \
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export VIV_SIM_USER_DO=$(MODELSIM_USER_DO); \
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export VIV_MODE=$(VIVADO_MODE); \
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export VIV_SIM_64BIT=$(MODELSIM_64BIT); \
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$(TOOLS_DIR)/scripts/launch_vivado.sh -mode $(VIVADO_MODE) -source $(call RESOLVE_PATH,$(TOOLS_DIR)/scripts/viv_sim_project.tcl) -log xsim.log -nojournal
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.SECONDEXPANSION:
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##xsim: Run the simulation using the Xilinx Vivado Simulator
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xsim: .check_tool $(DESIGN_SRCS) $(SIM_SRCS) $(INC_SRCS)
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$(call SETUP_AND_LAUNCH_SIMULATION,XSim)
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##xclean: Cleanup Xilinx Vivado Simulator intermediate files
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xclean:
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@rm -f xsim*.log
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@rm -rf xsim_proj
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@rm -f xvhdl.log
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@rm -f xvhdl.pba
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@rm -f xvlog.log
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@rm -f xvlog.pb
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@rm -f vivado_pid*.str
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##vsim: Run the simulation using ModelSim (via vivado)
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vsim: .check_tool $(COMPLIBDIR) $(DESIGN_SRCS) $(SIM_SRCS) $(INC_SRCS)
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$(call SETUP_AND_LAUNCH_SIMULATION,Modelsim)
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##modelsim: Run the simulation using Modelsim (natively)
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modelsim: .check_tool vlint
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cd $(MODELSIM_PROJ_DIR) && vsim $(MODELSIM_ARGS) $(foreach lib,$(MODELSIM_LIBS),-L $(lib)) $(SIM_TOP)
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# NOTE: VHDL files require a correct compile order. This script compiles files
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# in the order they are defined in $(DESIGN_SRC), then $SIM_SRC)
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##vlint: Run ModelSim compiler to lint files.
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vlint: .check_tool $(COMPLIBDIR) $(DESIGN_SRCS) $(SIM_SRCS) $(INC_SRCS)
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$(shell mkdir -p ./modelsim_proj)
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$(file >modelsim_proj/svlogarglist.txt,/* Auto generated argument file for vlog -sv */)
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$(file >>modelsim_proj/svlogarglist.txt,-sv)
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$(foreach dir,$(NOQ_INC_DIRS), $(file >>modelsim_proj/svlogarglist.txt,+incdir+$(dir)))
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$(foreach src,$(NOQ_PKG_SV), $(file >>modelsim_proj/svlogarglist.txt,$(src)))
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$(foreach src,$(NOQ_SV), $(file >>modelsim_proj/svlogarglist.txt,$(src)))
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$(file >modelsim_proj/vlogarglist.txt,/* Auto generated argument file for vlog */)
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$(file >>modelsim_proj/vlogarglist.txt,-vlog01compat)
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$(foreach dir,$(NOQ_INC_DIRS), $(file >>modelsim_proj/vlogarglist.txt,+incdir+$(dir)))
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$(foreach src,$(NOQ_VERILOG), $(file >>modelsim_proj/vlogarglist.txt,$(src)))
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$(file >modelsim_proj/vcomarglist.txt,/* Auto generated argument file for vcom */)
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$(file >>modelsim_proj/vcomarglist.txt,-2008)
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$(foreach src,$(NOQ_VHDL),$(file >>modelsim_proj/vcomarglist.txt,$(src)))
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ifneq ($(strip $(NOQ_SV)),)
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@echo "*** COMPILING SYSTEM VERILOG ***"
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cd $(MODELSIM_PROJ_DIR) && vlog $(SVLOG_ARGS) -f svlogarglist.txt
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endif
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ifneq ($(strip $(NOQ_VERILOG)),)
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@echo "*** COMPILING VERILOG ***"
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cd $(MODELSIM_PROJ_DIR) && vlog $(VLOG_ARGS) -f vlogarglist.txt
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endif
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ifneq ($(strip $(NOQ_VHDL)),)
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@echo "*** COMPILING VHDL ***"
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cd $(MODELSIM_PROJ_DIR) && vcom $(VHDL_ARGS) -f vcomarglist.txt
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endif
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##vclean: Cleanup ModelSim intermediate files
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vclean:
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@rm -f modelsim*.log
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@rm -rf modelsim_proj
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@rm -f vivado_pid*.str
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# Use clean with :: to support allow "make clean" to work with multiple makefiles
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clean:: xclean vclean
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help::
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@grep -h "##" $(abspath $(lastword $(MAKEFILE_LIST))) | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//'
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.PHONY: xsim xsim_hls xclean vsim vlint vclean clean help
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