Andrew Moch
b76ad2aef5
Adds LATENCY parameter to control the ammount of pieplineing. Adds a clock enable to control the advance of the pipeline. Used in xport when calculating new UDP headers for CHDR traffic. Original-commit: dd9847c5c3c3fac17658b526a7d8894711af086e
57 lines
1.4 KiB
Verilog
57 lines
1.4 KiB
Verilog
//
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// Copyright 2020 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Description:
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// Compute IP header checksum. 0-2 cycles of latency.
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//
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// Parameter:
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// LATENCY : sets how many pipeline stages are inserted
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// 0 - No pipelining
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// 1 - output Flop
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// 2 - output + gen_sum Flop
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//
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module ip_hdr_checksum #(
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parameter LATENCY = 2
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) (
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input clk, input [159:0] in, output reg [15:0] out, input clken
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);
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wire [18:0] padded [0:9];
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genvar i;
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generate
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for(i=0 ; i<10 ; i=i+1)
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assign padded[i] = {3'b000,in[i*16+15:i*16]};
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endgenerate
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wire [18:0] sum_a_d, sum_b_d;
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reg [18:0] sum_a_q, sum_b_q;
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assign sum_a_d = padded[0] + padded[1] + padded[2] + padded[3] + padded[4];
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assign sum_b_d = padded[5] + padded[6] + padded[7] + padded[8] + padded[9];
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if (LATENCY >= 1) begin : gen_sum_ff
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always @(posedge clk) if (clken) sum_a_q <= sum_a_d;
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always @(posedge clk) if (clken) sum_b_q <= sum_b_d;
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end else begin : gen_sum_comb
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always @(sum_a_d) sum_a_q = sum_a_d;
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always @(sum_b_d) sum_b_q = sum_b_d;
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end
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wire [18:0] sum;
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wire [15:0] out_d;
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assign sum = sum_a_q + sum_b_q;
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assign out_d = ~(sum[15:0] + {13'd0,sum[18:16]});
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if (LATENCY >= 2) begin : gen_out_ff
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always @(posedge clk) if (clken) out <= out_d;
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end else begin : gen_out_comb
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always @(out_d) out = out_d;
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end
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endmodule // ip_hdr_checksum
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