Martin Braun
8af1711952
The following modifications are applied to allow RFNoC blocks with zero input- or output ports (or none at all): - The backend interface will no longer synthesize any flushing logic if there are no streaming ports - The Mako templates are modified to allow generating code for blocks without streaming ports - The BFM for RFNoC blocks (RfnocBlockCtrlBfm) is partially factored out into a parent class (RfnocBlockCtrlBfmCtrlOnly) which allows the simulation of such RFNoC blocks Original-commit: 878cfcf48f125826e9d48b7c61a4ee7fd19e9a94
198 lines
8.0 KiB
Verilog
198 lines
8.0 KiB
Verilog
//
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// Copyright 2019 Ettus Research, A National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: backend_iface
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// Description:
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// A noc_shell interface to the backend infrastructure
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//
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// Parameters:
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// - CTRL_CLK_IDX: The index of the clock that is used for the control interface.
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// UHD will query this to generate a clock interface object for
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// the register interface. Set to 0 to let UHD figure this out
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// itself.
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// - TB_CLK_IDX: The index of the clock that is used as the timebase for this
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// block. UHD will query this to generate a clock interface object
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// for the register interface. This allows converting real-valued
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// timestamps into tick counts.
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module backend_iface #(
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parameter [31:0] NOC_ID = 32'h0,
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parameter [5:0] NUM_DATA_I = 0,
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parameter [5:0] NUM_DATA_O = 0,
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parameter [5:0] CTRL_FIFOSIZE = 0,
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parameter [7:0] CTRL_MAX_ASYNC_MSGS = 0,
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parameter [5:0] CTRL_CLK_IDX = 6'h3F,
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parameter [5:0] TB_CLK_IDX = 6'h3F,
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parameter [5:0] MTU = 0
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)(
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// Input clock
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input wire rfnoc_chdr_clk,
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input wire rfnoc_ctrl_clk,
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// Output reset
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output wire rfnoc_chdr_rst,
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output wire rfnoc_ctrl_rst,
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// Flush interface (sync. to rfnoc_chdr_clk)
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output wire data_i_flush_en,
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output wire [31:0] data_i_flush_timeout,
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input wire [63:0] data_i_flush_active,
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input wire [63:0] data_i_flush_done,
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output wire data_o_flush_en,
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output wire [31:0] data_o_flush_timeout,
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input wire [63:0] data_o_flush_active,
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input wire [63:0] data_o_flush_done,
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// Backend interface (sync. to rfnoc_ctrl_clk)
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input wire [511:0] rfnoc_core_config,
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output wire [511:0] rfnoc_core_status
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);
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localparam RESET_LENGTH = 32;
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`include "rfnoc_backend_iface.vh"
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// -----------------------------------
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// CONFIG: Infrastructure => Block
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// -----------------------------------
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wire [BEC_TOTAL_WIDTH-1:0] rfnoc_core_config_trim = rfnoc_core_config[BEC_TOTAL_WIDTH-1:0];
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// Synchronize flush signals to the CHDR clock domain. Note this is only
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// necessary if we have data ports.
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generate
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if (NUM_DATA_I > 0 || NUM_DATA_O > 0) begin
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reg [31:0] flush_timeout_ctclk = 32'd0;
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reg flush_en_ctclk = 1'b0;
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// Register logic before synchronizer
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always @(posedge rfnoc_ctrl_clk) begin
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flush_timeout_ctclk <= rfnoc_core_config_trim[BEC_FLUSH_TIMEOUT_OFFSET +: BEC_FLUSH_TIMEOUT_WIDTH];
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flush_en_ctclk <= rfnoc_core_config_trim[BEC_FLUSH_EN_OFFSET +: BEC_FLUSH_EN_WIDTH ];
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end
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// Synchronizer
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wire [31:0] flush_timeout_chclk;
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wire flush_en_chclk;
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// Note: We are using a synchronizer to cross the 32-bit timeout bus
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// into a different clock domain. Typically we would use a 2clk FIFO
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// but it's OK to have the bits unsynchronized here because the value
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// is static and is set from SW long before it is actually used.
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synchronizer #(.WIDTH(33), .INITIAL_VAL(33'd0)) sync_ctrl_i (
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.clk(rfnoc_chdr_clk), .rst(1'b0),
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.in({flush_en_ctclk, flush_timeout_ctclk}),
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.out({flush_en_chclk, flush_timeout_chclk})
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);
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assign data_i_flush_timeout = flush_timeout_chclk;
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assign data_o_flush_timeout = flush_timeout_chclk;
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assign data_i_flush_en = flush_en_chclk;
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assign data_o_flush_en = flush_en_chclk;
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end else begin
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assign data_i_flush_timeout = 32'h0;
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assign data_o_flush_timeout = 32'h0;
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assign data_i_flush_en = 1'b0;
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assign data_o_flush_en = 1'b0;
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end
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endgenerate
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// Synchronize the reset to the CHDR and CTRL clock domains, and extend the
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// reset pulse to make it long enough for most IP to reset correctly.
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reg soft_ctrl_rst_ctclk = 1'b0;
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reg soft_chdr_rst_ctclk = 1'b0;
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wire rfnoc_ctrl_rst_pulse;
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wire rfnoc_chdr_rst_pulse;
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// Register logic before synchronizer
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always @(posedge rfnoc_ctrl_clk) begin
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soft_ctrl_rst_ctclk <= rfnoc_core_config_trim[BEC_SOFT_CTRL_RST_OFFSET +: BEC_SOFT_CTRL_RST_WIDTH];
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soft_chdr_rst_ctclk <= rfnoc_core_config_trim[BEC_SOFT_CHDR_RST_OFFSET +: BEC_SOFT_CHDR_RST_WIDTH];
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end
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pulse_synchronizer #(.MODE("POSEDGE")) soft_ctrl_rst_sync_i (
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.clk_a(rfnoc_ctrl_clk), .rst_a(1'b0), .pulse_a(soft_ctrl_rst_ctclk), .busy_a(),
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.clk_b(rfnoc_ctrl_clk), .pulse_b(rfnoc_ctrl_rst_pulse)
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);
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pulse_synchronizer #(.MODE("POSEDGE")) soft_chdr_rst_sync_i (
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.clk_a(rfnoc_ctrl_clk), .rst_a(1'b0), .pulse_a(soft_chdr_rst_ctclk), .busy_a(),
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.clk_b(rfnoc_chdr_clk), .pulse_b(rfnoc_chdr_rst_pulse)
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);
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pulse_stretch_min #(.LENGTH(RESET_LENGTH)) soft_ctrl_rst_stretch_i (
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.clk(rfnoc_ctrl_clk), .rst(1'b0),
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.pulse_in(rfnoc_ctrl_rst_pulse), .pulse_out(rfnoc_ctrl_rst)
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);
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pulse_stretch_min #(.LENGTH(RESET_LENGTH)) soft_chdr_rst_stretch_i (
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.clk(rfnoc_chdr_clk), .rst(1'b0),
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.pulse_in(rfnoc_chdr_rst_pulse), .pulse_out(rfnoc_chdr_rst)
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);
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// -----------------------------------
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// STATUS: Block => Infrastructure
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// -----------------------------------
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generate
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if (NUM_DATA_I > 0 || NUM_DATA_O > 0) begin
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reg flush_active_chclk = 1'b0;
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reg flush_done_chclk = 1'b0;
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// Register logic before synchronizer
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wire flush_active_ctclk;
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wire flush_done_ctclk;
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if (NUM_DATA_I > 0 && NUM_DATA_O > 0) begin
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always @(posedge rfnoc_chdr_clk) begin
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flush_active_chclk <= (|data_i_flush_active[NUM_DATA_I-1:0]) | (|data_o_flush_active[NUM_DATA_O-1:0]);
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flush_done_chclk <= (&data_i_flush_done [NUM_DATA_I-1:0]) & (&data_o_flush_done [NUM_DATA_O-1:0]);
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end
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end else if (NUM_DATA_I > 0 && NUM_DATA_O == 0) begin
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always @(posedge rfnoc_chdr_clk) begin
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flush_active_chclk <= (|data_i_flush_active[NUM_DATA_I-1:0]);
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flush_done_chclk <= (&data_i_flush_done [NUM_DATA_I-1:0]);
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end
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end else if (NUM_DATA_I == 0 && NUM_DATA_O > 0) begin
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always @(posedge rfnoc_chdr_clk) begin
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flush_active_chclk <= (|data_o_flush_active[NUM_DATA_O-1:0]);
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flush_done_chclk <= (&data_o_flush_done [NUM_DATA_O-1:0]);
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end
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end
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// Synchronizer
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synchronizer #(.WIDTH(2), .INITIAL_VAL(2'd0)) sync_status_i (
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.clk(rfnoc_ctrl_clk), .rst(1'b0),
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.in({flush_active_chclk, flush_done_chclk}),
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.out({flush_active_ctclk, flush_done_ctclk})
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);
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assign rfnoc_core_status[BES_FLUSH_ACTIVE_OFFSET+:BES_FLUSH_ACTIVE_WIDTH] = flush_active_ctclk;
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assign rfnoc_core_status[BES_FLUSH_DONE_OFFSET +:BES_FLUSH_DONE_WIDTH ] = flush_done_ctclk;
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end else begin
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assign rfnoc_core_status[BES_FLUSH_ACTIVE_OFFSET+:BES_FLUSH_ACTIVE_WIDTH] = {BES_FLUSH_ACTIVE_WIDTH{1'b0}};
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assign rfnoc_core_status[BES_FLUSH_DONE_OFFSET +:BES_FLUSH_DONE_WIDTH ] = {BES_FLUSH_DONE_WIDTH{1'b1}};
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end
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endgenerate
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assign rfnoc_core_status[BES_PROTO_VER_OFFSET +:BES_PROTO_VER_WIDTH ] = BACKEND_PROTO_VER;
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assign rfnoc_core_status[BES_NUM_DATA_I_OFFSET +:BES_NUM_DATA_I_WIDTH ] = NUM_DATA_I;
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assign rfnoc_core_status[BES_NUM_DATA_O_OFFSET +:BES_NUM_DATA_O_WIDTH ] = NUM_DATA_O;
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assign rfnoc_core_status[BES_CTRL_FIFOSIZE_OFFSET +:BES_CTRL_FIFOSIZE_WIDTH ] = CTRL_FIFOSIZE;
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assign rfnoc_core_status[BES_CTRL_MAX_ASYNC_MSGS_OFFSET+:BES_CTRL_MAX_ASYNC_MSGS_WIDTH] = CTRL_MAX_ASYNC_MSGS;
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assign rfnoc_core_status[BES_NOC_ID_OFFSET +:BES_NOC_ID_WIDTH ] = NOC_ID;
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assign rfnoc_core_status[BES_DATA_MTU_OFFSET +:BES_DATA_MTU_WIDTH ] = MTU;
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assign rfnoc_core_status[BES_CTRL_CLK_IDX_OFFSET +:BES_CTRL_CLK_IDX_WIDTH ] = CTRL_CLK_IDX;
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assign rfnoc_core_status[BES_TB_CLK_IDX_OFFSET +:BES_TB_CLK_IDX_WIDTH ] = TB_CLK_IDX;
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// Assign the rest to 0
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assign rfnoc_core_status[511:BES_TOTAL_WIDTH] = {(512-BES_TOTAL_WIDTH){1'b0}};
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endmodule // backend_iface
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